1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_CONTROLQ_H_ 5 #define _ICE_CONTROLQ_H_ 6 7 #include "ice_adminq_cmd.h" 8 9 /* Maximum buffer lengths for all control queue types */ 10 #define ICE_AQ_MAX_BUF_LEN 4096 11 #define ICE_MBXQ_MAX_BUF_LEN 4096 12 13 #define ICE_CTL_Q_DESC(R, i) \ 14 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 15 16 #define ICE_CTL_Q_DESC_UNUSED(R) \ 17 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 18 (R)->next_to_clean - (R)->next_to_use - 1) 19 20 /* Defines that help manage the driver vs FW API checks. 21 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 22 */ 23 #define EXP_FW_API_VER_BRANCH 0x00 24 #define EXP_FW_API_VER_MAJOR 0x01 25 #define EXP_FW_API_VER_MINOR 0x05 26 27 /* Different control queue types: These are mainly for SW consumption. */ 28 enum ice_ctl_q { 29 ICE_CTL_Q_UNKNOWN = 0, 30 ICE_CTL_Q_ADMIN, 31 ICE_CTL_Q_MAILBOX, 32 }; 33 34 /* Control Queue timeout settings - max delay 1s */ 35 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */ 36 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ 37 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ 38 #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ 39 40 struct ice_ctl_q_ring { 41 void *dma_head; /* Virtual address to DMA head */ 42 struct ice_dma_mem desc_buf; /* descriptor ring memory */ 43 void *cmd_buf; /* command buffer memory */ 44 45 union { 46 struct ice_dma_mem *sq_bi; 47 struct ice_dma_mem *rq_bi; 48 } r; 49 50 u16 count; /* Number of descriptors */ 51 52 /* used for interrupt processing */ 53 u16 next_to_use; 54 u16 next_to_clean; 55 56 /* used for queue tracking */ 57 u32 head; 58 u32 tail; 59 u32 len; 60 u32 bah; 61 u32 bal; 62 u32 len_mask; 63 u32 len_ena_mask; 64 u32 len_crit_mask; 65 u32 head_mask; 66 }; 67 68 /* sq transaction details */ 69 struct ice_sq_cd { 70 struct ice_aq_desc *wb_desc; 71 }; 72 73 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 74 75 /* rq event information */ 76 struct ice_rq_event_info { 77 struct ice_aq_desc desc; 78 u16 msg_len; 79 u16 buf_len; 80 u8 *msg_buf; 81 }; 82 83 /* Control Queue information */ 84 struct ice_ctl_q_info { 85 enum ice_ctl_q qtype; 86 enum ice_aq_err rq_last_status; /* last status on receive queue */ 87 struct ice_ctl_q_ring rq; /* receive queue */ 88 struct ice_ctl_q_ring sq; /* send queue */ 89 u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 90 u16 num_rq_entries; /* receive queue depth */ 91 u16 num_sq_entries; /* send queue depth */ 92 u16 rq_buf_size; /* receive queue buffer size */ 93 u16 sq_buf_size; /* send queue buffer size */ 94 enum ice_aq_err sq_last_status; /* last status on send queue */ 95 struct mutex sq_lock; /* Send queue lock */ 96 struct mutex rq_lock; /* Receive queue lock */ 97 }; 98 99 #endif /* _ICE_CONTROLQ_H_ */ 100