1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 19 #define MTK_QDMA_PAGE_SIZE 2048 20 #define MTK_MAX_RX_LENGTH 1536 21 #define MTK_TX_DMA_BUF_LEN 0x3fff 22 #define MTK_DMA_SIZE 256 23 #define MTK_NAPI_WEIGHT 64 24 #define MTK_MAC_COUNT 2 25 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 26 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 27 #define MTK_DMA_DUMMY_DESC 0xffffffff 28 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 29 NETIF_MSG_PROBE | \ 30 NETIF_MSG_LINK | \ 31 NETIF_MSG_TIMER | \ 32 NETIF_MSG_IFDOWN | \ 33 NETIF_MSG_IFUP | \ 34 NETIF_MSG_RX_ERR | \ 35 NETIF_MSG_TX_ERR) 36 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 37 NETIF_F_RXCSUM | \ 38 NETIF_F_HW_VLAN_CTAG_TX | \ 39 NETIF_F_HW_VLAN_CTAG_RX | \ 40 NETIF_F_SG | NETIF_F_TSO | \ 41 NETIF_F_TSO6 | \ 42 NETIF_F_IPV6_CSUM) 43 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 44 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 45 46 #define MTK_MAX_RX_RING_NUM 4 47 #define MTK_HW_LRO_DMA_SIZE 8 48 49 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 50 #define MTK_MAX_LRO_IP_CNT 2 51 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 52 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 53 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 54 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 55 #define MTK_HW_LRO_MAX_AGG_CNT 64 56 #define MTK_HW_LRO_BW_THRE 3000 57 #define MTK_HW_LRO_REPLACE_DELTA 1000 58 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 59 60 /* Frame Engine Global Reset Register */ 61 #define MTK_RST_GL 0x04 62 #define RST_GL_PSE BIT(0) 63 64 /* Frame Engine Interrupt Status Register */ 65 #define MTK_INT_STATUS2 0x08 66 #define MTK_GDM1_AF BIT(28) 67 #define MTK_GDM2_AF BIT(29) 68 69 /* PDMA HW LRO Alter Flow Timer Register */ 70 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 71 72 /* Frame Engine Interrupt Grouping Register */ 73 #define MTK_FE_INT_GRP 0x20 74 75 /* CDMP Ingress Control Register */ 76 #define MTK_CDMQ_IG_CTRL 0x1400 77 #define MTK_CDMQ_STAG_EN BIT(0) 78 79 /* CDMP Exgress Control Register */ 80 #define MTK_CDMP_EG_CTRL 0x404 81 82 /* GDM Exgress Control Register */ 83 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 84 #define MTK_GDMA_ICS_EN BIT(22) 85 #define MTK_GDMA_TCS_EN BIT(21) 86 #define MTK_GDMA_UCS_EN BIT(20) 87 #define MTK_GDMA_TO_PDMA 0x0 88 #define MTK_GDMA_DROP_ALL 0x7777 89 90 /* Unicast Filter MAC Address Register - Low */ 91 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 92 93 /* Unicast Filter MAC Address Register - High */ 94 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 95 96 /* PDMA RX Base Pointer Register */ 97 #define MTK_PRX_BASE_PTR0 0x900 98 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 99 100 /* PDMA RX Maximum Count Register */ 101 #define MTK_PRX_MAX_CNT0 0x904 102 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 103 104 /* PDMA RX CPU Pointer Register */ 105 #define MTK_PRX_CRX_IDX0 0x908 106 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 107 108 /* PDMA HW LRO Control Registers */ 109 #define MTK_PDMA_LRO_CTRL_DW0 0x980 110 #define MTK_LRO_EN BIT(0) 111 #define MTK_L3_CKS_UPD_EN BIT(7) 112 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 113 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 114 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 115 116 #define MTK_PDMA_LRO_CTRL_DW1 0x984 117 #define MTK_PDMA_LRO_CTRL_DW2 0x988 118 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 119 #define MTK_ADMA_MODE BIT(15) 120 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 121 122 /* PDMA Global Configuration Register */ 123 #define MTK_PDMA_GLO_CFG 0xa04 124 #define MTK_MULTI_EN BIT(10) 125 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 126 127 /* PDMA Reset Index Register */ 128 #define MTK_PDMA_RST_IDX 0xa08 129 #define MTK_PST_DRX_IDX0 BIT(16) 130 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 131 132 /* PDMA Delay Interrupt Register */ 133 #define MTK_PDMA_DELAY_INT 0xa0c 134 #define MTK_PDMA_DELAY_RX_EN BIT(15) 135 #define MTK_PDMA_DELAY_RX_PINT 4 136 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 137 #define MTK_PDMA_DELAY_RX_PTIME 4 138 #define MTK_PDMA_DELAY_RX_DELAY \ 139 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 140 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 141 142 /* PDMA Interrupt Status Register */ 143 #define MTK_PDMA_INT_STATUS 0xa20 144 145 /* PDMA Interrupt Mask Register */ 146 #define MTK_PDMA_INT_MASK 0xa28 147 148 /* PDMA HW LRO Alter Flow Delta Register */ 149 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 150 151 /* PDMA Interrupt grouping registers */ 152 #define MTK_PDMA_INT_GRP1 0xa50 153 #define MTK_PDMA_INT_GRP2 0xa54 154 155 /* PDMA HW LRO IP Setting Registers */ 156 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 157 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 158 #define MTK_RING_MYIP_VLD BIT(9) 159 160 /* PDMA HW LRO Ring Control Registers */ 161 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 162 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 163 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 164 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 165 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 166 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 167 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 168 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 169 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 170 #define MTK_RING_VLD BIT(8) 171 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 172 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 173 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 174 175 /* QDMA TX Queue Configuration Registers */ 176 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 177 #define QDMA_RES_THRES 4 178 179 /* QDMA TX Queue Scheduler Registers */ 180 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 181 182 /* QDMA RX Base Pointer Register */ 183 #define MTK_QRX_BASE_PTR0 0x1900 184 185 /* QDMA RX Maximum Count Register */ 186 #define MTK_QRX_MAX_CNT0 0x1904 187 188 /* QDMA RX CPU Pointer Register */ 189 #define MTK_QRX_CRX_IDX0 0x1908 190 191 /* QDMA RX DMA Pointer Register */ 192 #define MTK_QRX_DRX_IDX0 0x190C 193 194 /* QDMA Global Configuration Register */ 195 #define MTK_QDMA_GLO_CFG 0x1A04 196 #define MTK_RX_2B_OFFSET BIT(31) 197 #define MTK_RX_BT_32DWORDS (3 << 11) 198 #define MTK_NDP_CO_PRO BIT(10) 199 #define MTK_TX_WB_DDONE BIT(6) 200 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 201 #define MTK_RX_DMA_BUSY BIT(3) 202 #define MTK_TX_DMA_BUSY BIT(1) 203 #define MTK_RX_DMA_EN BIT(2) 204 #define MTK_TX_DMA_EN BIT(0) 205 #define MTK_DMA_BUSY_TIMEOUT HZ 206 207 /* QDMA Reset Index Register */ 208 #define MTK_QDMA_RST_IDX 0x1A08 209 210 /* QDMA Delay Interrupt Register */ 211 #define MTK_QDMA_DELAY_INT 0x1A0C 212 213 /* QDMA Flow Control Register */ 214 #define MTK_QDMA_FC_THRES 0x1A10 215 #define FC_THRES_DROP_MODE BIT(20) 216 #define FC_THRES_DROP_EN (7 << 16) 217 #define FC_THRES_MIN 0x4444 218 219 /* QDMA Interrupt Status Register */ 220 #define MTK_QDMA_INT_STATUS 0x1A18 221 #define MTK_RX_DONE_DLY BIT(30) 222 #define MTK_RX_DONE_INT3 BIT(19) 223 #define MTK_RX_DONE_INT2 BIT(18) 224 #define MTK_RX_DONE_INT1 BIT(17) 225 #define MTK_RX_DONE_INT0 BIT(16) 226 #define MTK_TX_DONE_INT3 BIT(3) 227 #define MTK_TX_DONE_INT2 BIT(2) 228 #define MTK_TX_DONE_INT1 BIT(1) 229 #define MTK_TX_DONE_INT0 BIT(0) 230 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 231 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 232 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 233 234 /* QDMA Interrupt grouping registers */ 235 #define MTK_QDMA_INT_GRP1 0x1a20 236 #define MTK_QDMA_INT_GRP2 0x1a24 237 #define MTK_RLS_DONE_INT BIT(0) 238 239 /* QDMA Interrupt Status Register */ 240 #define MTK_QDMA_INT_MASK 0x1A1C 241 242 /* QDMA Interrupt Mask Register */ 243 #define MTK_QDMA_HRED2 0x1A44 244 245 /* QDMA TX Forward CPU Pointer Register */ 246 #define MTK_QTX_CTX_PTR 0x1B00 247 248 /* QDMA TX Forward DMA Pointer Register */ 249 #define MTK_QTX_DTX_PTR 0x1B04 250 251 /* QDMA TX Release CPU Pointer Register */ 252 #define MTK_QTX_CRX_PTR 0x1B10 253 254 /* QDMA TX Release DMA Pointer Register */ 255 #define MTK_QTX_DRX_PTR 0x1B14 256 257 /* QDMA FQ Head Pointer Register */ 258 #define MTK_QDMA_FQ_HEAD 0x1B20 259 260 /* QDMA FQ Head Pointer Register */ 261 #define MTK_QDMA_FQ_TAIL 0x1B24 262 263 /* QDMA FQ Free Page Counter Register */ 264 #define MTK_QDMA_FQ_CNT 0x1B28 265 266 /* QDMA FQ Free Page Buffer Length Register */ 267 #define MTK_QDMA_FQ_BLEN 0x1B2C 268 269 /* GMA1 counter / statics register */ 270 #define MTK_GDM1_RX_GBCNT_L 0x2400 271 #define MTK_GDM1_RX_GBCNT_H 0x2404 272 #define MTK_GDM1_RX_GPCNT 0x2408 273 #define MTK_GDM1_RX_OERCNT 0x2410 274 #define MTK_GDM1_RX_FERCNT 0x2414 275 #define MTK_GDM1_RX_SERCNT 0x2418 276 #define MTK_GDM1_RX_LENCNT 0x241c 277 #define MTK_GDM1_RX_CERCNT 0x2420 278 #define MTK_GDM1_RX_FCCNT 0x2424 279 #define MTK_GDM1_TX_SKIPCNT 0x2428 280 #define MTK_GDM1_TX_COLCNT 0x242c 281 #define MTK_GDM1_TX_GBCNT_L 0x2430 282 #define MTK_GDM1_TX_GBCNT_H 0x2434 283 #define MTK_GDM1_TX_GPCNT 0x2438 284 #define MTK_STAT_OFFSET 0x40 285 286 /* QDMA descriptor txd4 */ 287 #define TX_DMA_CHKSUM (0x7 << 29) 288 #define TX_DMA_TSO BIT(28) 289 #define TX_DMA_FPORT_SHIFT 25 290 #define TX_DMA_FPORT_MASK 0x7 291 #define TX_DMA_INS_VLAN BIT(16) 292 293 /* QDMA descriptor txd3 */ 294 #define TX_DMA_OWNER_CPU BIT(31) 295 #define TX_DMA_LS0 BIT(30) 296 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 297 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 298 #define TX_DMA_SWC BIT(14) 299 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 300 301 /* PDMA on MT7628 */ 302 #define TX_DMA_DONE BIT(31) 303 #define TX_DMA_LS1 BIT(14) 304 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 305 306 /* QDMA descriptor rxd2 */ 307 #define RX_DMA_DONE BIT(31) 308 #define RX_DMA_LSO BIT(30) 309 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 310 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 311 #define RX_DMA_VTAG BIT(15) 312 313 /* QDMA descriptor rxd3 */ 314 #define RX_DMA_VID(_x) ((_x) & 0xfff) 315 316 /* QDMA descriptor rxd4 */ 317 #define RX_DMA_L4_VALID BIT(24) 318 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 319 #define RX_DMA_FPORT_SHIFT 19 320 #define RX_DMA_FPORT_MASK 0x7 321 322 /* PHY Indirect Access Control registers */ 323 #define MTK_PHY_IAC 0x10004 324 #define PHY_IAC_ACCESS BIT(31) 325 #define PHY_IAC_READ BIT(19) 326 #define PHY_IAC_WRITE BIT(18) 327 #define PHY_IAC_START BIT(16) 328 #define PHY_IAC_ADDR_SHIFT 20 329 #define PHY_IAC_REG_SHIFT 25 330 #define PHY_IAC_TIMEOUT HZ 331 332 #define MTK_MAC_MISC 0x1000c 333 #define MTK_MUX_TO_ESW BIT(0) 334 335 /* Mac control registers */ 336 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 337 #define MAC_MCR_MAX_RX_1536 BIT(24) 338 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 339 #define MAC_MCR_FORCE_MODE BIT(15) 340 #define MAC_MCR_TX_EN BIT(14) 341 #define MAC_MCR_RX_EN BIT(13) 342 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 343 #define MAC_MCR_BACKOFF_EN BIT(9) 344 #define MAC_MCR_BACKPR_EN BIT(8) 345 #define MAC_MCR_FORCE_RX_FC BIT(5) 346 #define MAC_MCR_FORCE_TX_FC BIT(4) 347 #define MAC_MCR_SPEED_1000 BIT(3) 348 #define MAC_MCR_SPEED_100 BIT(2) 349 #define MAC_MCR_FORCE_DPX BIT(1) 350 #define MAC_MCR_FORCE_LINK BIT(0) 351 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 352 353 /* Mac status registers */ 354 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 355 #define MAC_MSR_EEE1G BIT(7) 356 #define MAC_MSR_EEE100M BIT(6) 357 #define MAC_MSR_RX_FC BIT(5) 358 #define MAC_MSR_TX_FC BIT(4) 359 #define MAC_MSR_SPEED_1000 BIT(3) 360 #define MAC_MSR_SPEED_100 BIT(2) 361 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 362 #define MAC_MSR_DPX BIT(1) 363 #define MAC_MSR_LINK BIT(0) 364 365 /* TRGMII RXC control register */ 366 #define TRGMII_RCK_CTRL 0x10300 367 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 368 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 369 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 370 #define RXC_RST BIT(31) 371 #define RXC_DQSISEL BIT(30) 372 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 373 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 374 375 #define NUM_TRGMII_CTRL 5 376 377 /* TRGMII RXC control register */ 378 #define TRGMII_TCK_CTRL 0x10340 379 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 380 #define TXC_INV BIT(30) 381 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 382 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 383 384 /* TRGMII TX Drive Strength */ 385 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 386 #define TD_DM_DRVP(x) ((x) & 0xf) 387 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 388 389 /* TRGMII Interface mode register */ 390 #define INTF_MODE 0x10390 391 #define TRGMII_INTF_DIS BIT(0) 392 #define TRGMII_MODE BIT(1) 393 #define TRGMII_CENTRAL_ALIGNED BIT(2) 394 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 395 #define INTF_MODE_RGMII_10_100 0 396 397 /* GPIO port control registers for GMAC 2*/ 398 #define GPIO_OD33_CTRL8 0x4c0 399 #define GPIO_BIAS_CTRL 0xed0 400 #define GPIO_DRV_SEL10 0xf00 401 402 /* ethernet subsystem chip id register */ 403 #define ETHSYS_CHIPID0_3 0x0 404 #define ETHSYS_CHIPID4_7 0x4 405 #define MT7623_ETH 7623 406 #define MT7622_ETH 7622 407 #define MT7621_ETH 7621 408 409 /* ethernet system control register */ 410 #define ETHSYS_SYSCFG 0x10 411 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 412 413 /* ethernet subsystem config register */ 414 #define ETHSYS_SYSCFG0 0x14 415 #define SYSCFG0_GE_MASK 0x3 416 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 417 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 418 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 419 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 420 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 421 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 422 423 424 /* ethernet subsystem clock register */ 425 #define ETHSYS_CLKCFG0 0x2c 426 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 427 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 428 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 429 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 430 431 /* ethernet reset control register */ 432 #define ETHSYS_RSTCTRL 0x34 433 #define RSTCTRL_FE BIT(6) 434 #define RSTCTRL_PPE BIT(31) 435 436 /* SGMII subsystem config registers */ 437 /* Register to auto-negotiation restart */ 438 #define SGMSYS_PCS_CONTROL_1 0x0 439 #define SGMII_AN_RESTART BIT(9) 440 #define SGMII_ISOLATE BIT(10) 441 #define SGMII_AN_ENABLE BIT(12) 442 #define SGMII_LINK_STATYS BIT(18) 443 #define SGMII_AN_ABILITY BIT(19) 444 #define SGMII_AN_COMPLETE BIT(21) 445 #define SGMII_PCS_FAULT BIT(23) 446 #define SGMII_AN_EXPANSION_CLR BIT(30) 447 448 /* Register to programmable link timer, the unit in 2 * 8ns */ 449 #define SGMSYS_PCS_LINK_TIMER 0x18 450 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 451 452 /* Register to control remote fault */ 453 #define SGMSYS_SGMII_MODE 0x20 454 #define SGMII_IF_MODE_BIT0 BIT(0) 455 #define SGMII_SPEED_DUPLEX_AN BIT(1) 456 #define SGMII_SPEED_10 0x0 457 #define SGMII_SPEED_100 BIT(2) 458 #define SGMII_SPEED_1000 BIT(3) 459 #define SGMII_DUPLEX_FULL BIT(4) 460 #define SGMII_IF_MODE_BIT5 BIT(5) 461 #define SGMII_REMOTE_FAULT_DIS BIT(8) 462 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 463 #define SGMII_CODE_SYNC_SET_EN BIT(10) 464 #define SGMII_SEND_AN_ERROR_EN BIT(11) 465 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 466 467 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 468 #define SGMSYS_ANA_RG_CS3 0x2028 469 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 470 #define RG_PHY_SPEED_1_25G 0x0 471 #define RG_PHY_SPEED_3_125G BIT(2) 472 473 /* Register to power up QPHY */ 474 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 475 #define SGMII_PHYA_PWD BIT(4) 476 477 /* Infrasys subsystem config registers */ 478 #define INFRA_MISC2 0x70c 479 #define CO_QPHY_SEL BIT(0) 480 #define GEPHY_MAC_SEL BIT(1) 481 482 /* MT7628/88 specific stuff */ 483 #define MT7628_PDMA_OFFSET 0x0800 484 #define MT7628_SDM_OFFSET 0x0c00 485 486 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 487 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 488 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 489 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 490 #define MT7628_PST_DTX_IDX0 BIT(0) 491 492 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 493 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 494 495 /* Counter / stat register */ 496 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 497 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 498 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 499 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 500 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 501 502 struct mtk_rx_dma { 503 unsigned int rxd1; 504 unsigned int rxd2; 505 unsigned int rxd3; 506 unsigned int rxd4; 507 } __packed __aligned(4); 508 509 struct mtk_tx_dma { 510 unsigned int txd1; 511 unsigned int txd2; 512 unsigned int txd3; 513 unsigned int txd4; 514 } __packed __aligned(4); 515 516 struct mtk_eth; 517 struct mtk_mac; 518 519 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 520 * @stats_lock: make sure that stats operations are atomic 521 * @reg_offset: the status register offset of the SoC 522 * @syncp: the refcount 523 * 524 * All of the supported SoCs have hardware counters for traffic statistics. 525 * Whenever the status IRQ triggers we can read the latest stats from these 526 * counters and store them in this struct. 527 */ 528 struct mtk_hw_stats { 529 u64 tx_bytes; 530 u64 tx_packets; 531 u64 tx_skip; 532 u64 tx_collisions; 533 u64 rx_bytes; 534 u64 rx_packets; 535 u64 rx_overflow; 536 u64 rx_fcs_errors; 537 u64 rx_short_errors; 538 u64 rx_long_errors; 539 u64 rx_checksum_errors; 540 u64 rx_flow_control_packets; 541 542 spinlock_t stats_lock; 543 u32 reg_offset; 544 struct u64_stats_sync syncp; 545 }; 546 547 enum mtk_tx_flags { 548 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 549 * track how memory was allocated so that it can be freed properly. 550 */ 551 MTK_TX_FLAGS_SINGLE0 = 0x01, 552 MTK_TX_FLAGS_PAGE0 = 0x02, 553 554 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 555 * SKB out instead of looking up through hardware TX descriptor. 556 */ 557 MTK_TX_FLAGS_FPORT0 = 0x04, 558 MTK_TX_FLAGS_FPORT1 = 0x08, 559 }; 560 561 /* This enum allows us to identify how the clock is defined on the array of the 562 * clock in the order 563 */ 564 enum mtk_clks_map { 565 MTK_CLK_ETHIF, 566 MTK_CLK_SGMIITOP, 567 MTK_CLK_ESW, 568 MTK_CLK_GP0, 569 MTK_CLK_GP1, 570 MTK_CLK_GP2, 571 MTK_CLK_FE, 572 MTK_CLK_TRGPLL, 573 MTK_CLK_SGMII_TX_250M, 574 MTK_CLK_SGMII_RX_250M, 575 MTK_CLK_SGMII_CDR_REF, 576 MTK_CLK_SGMII_CDR_FB, 577 MTK_CLK_SGMII2_TX_250M, 578 MTK_CLK_SGMII2_RX_250M, 579 MTK_CLK_SGMII2_CDR_REF, 580 MTK_CLK_SGMII2_CDR_FB, 581 MTK_CLK_SGMII_CK, 582 MTK_CLK_ETH2PLL, 583 MTK_CLK_MAX 584 }; 585 586 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 587 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 588 BIT(MTK_CLK_TRGPLL)) 589 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 590 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 591 BIT(MTK_CLK_GP2) | \ 592 BIT(MTK_CLK_SGMII_TX_250M) | \ 593 BIT(MTK_CLK_SGMII_RX_250M) | \ 594 BIT(MTK_CLK_SGMII_CDR_REF) | \ 595 BIT(MTK_CLK_SGMII_CDR_FB) | \ 596 BIT(MTK_CLK_SGMII_CK) | \ 597 BIT(MTK_CLK_ETH2PLL)) 598 #define MT7621_CLKS_BITMAP (0) 599 #define MT7628_CLKS_BITMAP (0) 600 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 601 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 602 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 603 BIT(MTK_CLK_SGMII_TX_250M) | \ 604 BIT(MTK_CLK_SGMII_RX_250M) | \ 605 BIT(MTK_CLK_SGMII_CDR_REF) | \ 606 BIT(MTK_CLK_SGMII_CDR_FB) | \ 607 BIT(MTK_CLK_SGMII2_TX_250M) | \ 608 BIT(MTK_CLK_SGMII2_RX_250M) | \ 609 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 610 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 611 BIT(MTK_CLK_SGMII_CK) | \ 612 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 613 614 enum mtk_dev_state { 615 MTK_HW_INIT, 616 MTK_RESETTING 617 }; 618 619 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 620 * by the TX descriptor s 621 * @skb: The SKB pointer of the packet being sent 622 * @dma_addr0: The base addr of the first segment 623 * @dma_len0: The length of the first segment 624 * @dma_addr1: The base addr of the second segment 625 * @dma_len1: The length of the second segment 626 */ 627 struct mtk_tx_buf { 628 struct sk_buff *skb; 629 u32 flags; 630 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 631 DEFINE_DMA_UNMAP_LEN(dma_len0); 632 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 633 DEFINE_DMA_UNMAP_LEN(dma_len1); 634 }; 635 636 /* struct mtk_tx_ring - This struct holds info describing a TX ring 637 * @dma: The descriptor ring 638 * @buf: The memory pointed at by the ring 639 * @phys: The physical addr of tx_buf 640 * @next_free: Pointer to the next free descriptor 641 * @last_free: Pointer to the last free descriptor 642 * @thresh: The threshold of minimum amount of free descriptors 643 * @free_count: QDMA uses a linked list. Track how many free descriptors 644 * are present 645 */ 646 struct mtk_tx_ring { 647 struct mtk_tx_dma *dma; 648 struct mtk_tx_buf *buf; 649 dma_addr_t phys; 650 struct mtk_tx_dma *next_free; 651 struct mtk_tx_dma *last_free; 652 u16 thresh; 653 atomic_t free_count; 654 int dma_size; 655 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 656 dma_addr_t phys_pdma; 657 int cpu_idx; 658 }; 659 660 /* PDMA rx ring mode */ 661 enum mtk_rx_flags { 662 MTK_RX_FLAGS_NORMAL = 0, 663 MTK_RX_FLAGS_HWLRO, 664 MTK_RX_FLAGS_QDMA, 665 }; 666 667 /* struct mtk_rx_ring - This struct holds info describing a RX ring 668 * @dma: The descriptor ring 669 * @data: The memory pointed at by the ring 670 * @phys: The physical addr of rx_buf 671 * @frag_size: How big can each fragment be 672 * @buf_size: The size of each packet buffer 673 * @calc_idx: The current head of ring 674 */ 675 struct mtk_rx_ring { 676 struct mtk_rx_dma *dma; 677 u8 **data; 678 dma_addr_t phys; 679 u16 frag_size; 680 u16 buf_size; 681 u16 dma_size; 682 bool calc_idx_update; 683 u16 calc_idx; 684 u32 crx_idx_reg; 685 }; 686 687 enum mkt_eth_capabilities { 688 MTK_RGMII_BIT = 0, 689 MTK_TRGMII_BIT, 690 MTK_SGMII_BIT, 691 MTK_ESW_BIT, 692 MTK_GEPHY_BIT, 693 MTK_MUX_BIT, 694 MTK_INFRA_BIT, 695 MTK_SHARED_SGMII_BIT, 696 MTK_HWLRO_BIT, 697 MTK_SHARED_INT_BIT, 698 MTK_TRGMII_MT7621_CLK_BIT, 699 MTK_QDMA_BIT, 700 MTK_SOC_MT7628_BIT, 701 702 /* MUX BITS*/ 703 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 704 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 705 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 706 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 707 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 708 709 /* PATH BITS */ 710 MTK_ETH_PATH_GMAC1_RGMII_BIT, 711 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 712 MTK_ETH_PATH_GMAC1_SGMII_BIT, 713 MTK_ETH_PATH_GMAC2_RGMII_BIT, 714 MTK_ETH_PATH_GMAC2_SGMII_BIT, 715 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 716 MTK_ETH_PATH_GDM1_ESW_BIT, 717 }; 718 719 /* Supported hardware group on SoCs */ 720 #define MTK_RGMII BIT(MTK_RGMII_BIT) 721 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 722 #define MTK_SGMII BIT(MTK_SGMII_BIT) 723 #define MTK_ESW BIT(MTK_ESW_BIT) 724 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 725 #define MTK_MUX BIT(MTK_MUX_BIT) 726 #define MTK_INFRA BIT(MTK_INFRA_BIT) 727 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 728 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 729 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 730 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 731 #define MTK_QDMA BIT(MTK_QDMA_BIT) 732 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 733 734 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 735 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 736 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 737 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 738 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 739 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 740 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 741 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 742 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 743 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 744 745 /* Supported path present on SoCs */ 746 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 747 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 748 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 749 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 750 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 751 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 752 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 753 754 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 755 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 756 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 757 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 758 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 759 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 760 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 761 762 /* MUXes present on SoCs */ 763 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 764 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 765 766 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 767 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 768 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 769 770 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 771 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 772 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 773 774 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 775 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 776 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 777 MTK_SHARED_SGMII) 778 779 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 780 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 781 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 782 783 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 784 785 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 786 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 787 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 788 789 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 790 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 791 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 792 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 793 794 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 795 MTK_QDMA) 796 797 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 798 799 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 800 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 801 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 802 MTK_MUX_U3_GMAC2_TO_QPHY | \ 803 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 804 805 /* struct mtk_eth_data - This is the structure holding all differences 806 * among various plaforms 807 * @ana_rgc3: The offset for register ANA_RGC3 related to 808 * sgmiisys syscon 809 * @caps Flags shown the extra capability for the SoC 810 * @hw_features Flags shown HW features 811 * @required_clks Flags shown the bitmap for required clocks on 812 * the target SoC 813 * @required_pctl A bool value to show whether the SoC requires 814 * the extra setup for those pins used by GMAC. 815 */ 816 struct mtk_soc_data { 817 u32 ana_rgc3; 818 u32 caps; 819 u32 required_clks; 820 bool required_pctl; 821 netdev_features_t hw_features; 822 }; 823 824 /* currently no SoC has more than 2 macs */ 825 #define MTK_MAX_DEVS 2 826 827 #define MTK_SGMII_PHYSPEED_AN BIT(31) 828 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 829 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 830 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 831 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 832 833 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 834 * characteristics 835 * @regmap: The register map pointing at the range used to setup 836 * SGMII modes 837 * @flags: The enum refers to which mode the sgmii wants to run on 838 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 839 */ 840 841 struct mtk_sgmii { 842 struct regmap *regmap[MTK_MAX_DEVS]; 843 u32 flags[MTK_MAX_DEVS]; 844 u32 ana_rgc3; 845 }; 846 847 /* struct mtk_eth - This is the main datasructure for holding the state 848 * of the driver 849 * @dev: The device pointer 850 * @base: The mapped register i/o base 851 * @page_lock: Make sure that register operations are atomic 852 * @tx_irq__lock: Make sure that IRQ register operations are atomic 853 * @rx_irq__lock: Make sure that IRQ register operations are atomic 854 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 855 * dummy for NAPI to work 856 * @netdev: The netdev instances 857 * @mac: Each netdev is linked to a physical MAC 858 * @irq: The IRQ that we are using 859 * @msg_enable: Ethtool msg level 860 * @ethsys: The register map pointing at the range used to setup 861 * MII modes 862 * @infra: The register map pointing at the range used to setup 863 * SGMII and GePHY path 864 * @pctl: The register map pointing at the range used to setup 865 * GMAC port drive/slew values 866 * @dma_refcnt: track how many netdevs are using the DMA engine 867 * @tx_ring: Pointer to the memory holding info about the TX ring 868 * @rx_ring: Pointer to the memory holding info about the RX ring 869 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 870 * @tx_napi: The TX NAPI struct 871 * @rx_napi: The RX NAPI struct 872 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 873 * @phy_scratch_ring: physical address of scratch_ring 874 * @scratch_head: The scratch memory that scratch_ring points to. 875 * @clks: clock array for all clocks required 876 * @mii_bus: If there is a bus we need to create an instance for it 877 * @pending_work: The workqueue used to reset the dma ring 878 * @state: Initialization and runtime state of the device 879 * @soc: Holding specific data among vaious SoCs 880 */ 881 882 struct mtk_eth { 883 struct device *dev; 884 void __iomem *base; 885 spinlock_t page_lock; 886 spinlock_t tx_irq_lock; 887 spinlock_t rx_irq_lock; 888 struct net_device dummy_dev; 889 struct net_device *netdev[MTK_MAX_DEVS]; 890 struct mtk_mac *mac[MTK_MAX_DEVS]; 891 int irq[3]; 892 u32 msg_enable; 893 unsigned long sysclk; 894 struct regmap *ethsys; 895 struct regmap *infra; 896 struct mtk_sgmii *sgmii; 897 struct regmap *pctl; 898 bool hwlro; 899 refcount_t dma_refcnt; 900 struct mtk_tx_ring tx_ring; 901 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 902 struct mtk_rx_ring rx_ring_qdma; 903 struct napi_struct tx_napi; 904 struct napi_struct rx_napi; 905 struct mtk_tx_dma *scratch_ring; 906 dma_addr_t phy_scratch_ring; 907 void *scratch_head; 908 struct clk *clks[MTK_CLK_MAX]; 909 910 struct mii_bus *mii_bus; 911 struct work_struct pending_work; 912 unsigned long state; 913 914 const struct mtk_soc_data *soc; 915 916 u32 tx_int_mask_reg; 917 u32 tx_int_status_reg; 918 u32 rx_dma_l4_valid; 919 int ip_align; 920 }; 921 922 /* struct mtk_mac - the structure that holds the info about the MACs of the 923 * SoC 924 * @id: The number of the MAC 925 * @interface: Interface mode kept for detecting change in hw settings 926 * @of_node: Our devicetree node 927 * @hw: Backpointer to our main datastruture 928 * @hw_stats: Packet statistics counter 929 */ 930 struct mtk_mac { 931 int id; 932 phy_interface_t interface; 933 unsigned int mode; 934 int speed; 935 struct device_node *of_node; 936 struct phylink *phylink; 937 struct phylink_config phylink_config; 938 struct mtk_eth *hw; 939 struct mtk_hw_stats *hw_stats; 940 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 941 int hwlro_ip_cnt; 942 }; 943 944 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 945 extern const struct of_device_id of_mtk_match[]; 946 947 /* read the hardware status register */ 948 void mtk_stats_update_mac(struct mtk_mac *mac); 949 950 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 951 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 952 953 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 954 u32 ana_rgc3); 955 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 956 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 957 const struct phylink_link_state *state); 958 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 959 960 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 961 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 962 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 963 964 #endif /* MTK_ETH_H */ 965