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Searched refs:A6XX_GMU_IRQ_MASK (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gmu.c822 #define A6XX_GMU_IRQ_MASK \ macro
931 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); in a6xx_gmu_resume()