Searched refs:Array (Results 1 – 13 of 13) sorted by relevance
264 u32 *Array = Array_MP_8723B_AGC_TAB; in ODM_ReadAndConfig_MP_8723B_AGC_TAB() local274 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB()275 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB()533 u32 *Array = Array_MP_8723B_PHY_REG; in ODM_ReadAndConfig_MP_8723B_PHY_REG() local543 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG()544 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_PHY_REG()612 u32 *Array = Array_MP_8723B_PHY_REG_PG; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG() local625 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()626 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()627 u32 v3 = Array[i+2]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()[all …]
266 u32 *Array = Array_MP_8723B_RadioA; in ODM_ReadAndConfig_MP_8723B_RadioA() local276 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_RadioA()277 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_RadioA()761 u8 **Array = Array_MP_8723B_TXPWR_LMT; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT() local771 u8 *regulation = Array[i]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()772 u8 *band = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()773 u8 *bandwidth = Array[i+2]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()774 u8 *rate = Array[i+3]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()775 u8 *rfPath = Array[i+4]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()776 u8 *chnl = Array[i+5]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()[all …]
235 u32 *Array = Array_MP_8723B_MAC_REG; in ODM_ReadAndConfig_MP_8723B_MAC_REG() local245 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_MAC_REG()246 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_MAC_REG()
90 …EXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } whi…
1699 u32 *Array = Array_kfreemap; in rtw_bb_rf_gain_offset() local1712 v1 = Array[i]; in rtw_bb_rf_gain_offset()1713 v2 = Array[i+1]; in rtw_bb_rf_gain_offset()
45 One Block of the NAND Flash Array memory is reserved as47 Also, 1st Block of NAND Flash Array can be used as OTP.50 operations as any other NAND Flash Array memory block.
87 ALR8580 "Advanced Disk Array Caching EISA Controller"233 CPQ4001 "Compaq 32-Bit Intelligent Drive Array Controller"234 CPQ4002 "Compaq Intelligent Drive Array Controller-2"235 CPQ4010 "Compaq 32-Bit Intelligent Drive Array Expansion Controller"236 CPQ4020 "Compaq SMART Array Controller"237 CPQ4030 "Compaq SMART-2/E Array Controller"477 DEL4001 "Dell Drive Array"478 DEL4002 "Dell SCSI Array Controller"1056 ISADF03 "Weitek Array Processor, Brd #3002-0046-01"1102 MLX0070 "Mylex DAC960 EISA Disk Array Controller"[all …]
21 An FPGA (Field Programmable Gate Array) is a programmable hardware that is
155 Gate Array (FPGA) solutions which implement Device Feature List.200 Field-Programmable Gate Array (FPGA) solutions which implement
332 tristate "HP Smart Array SCSI driver"337 This driver supports HP Smart Array Controllers (circa 2009).339 driver. Anyone wishing to use HP Smart Array controllers who673 tristate "Intel/ICP (former GDT SCSI Disk Array) RAID Controller support"676 Formerly called GDT SCSI Disk Array Controller Support.678 This is a driver for RAID/SCSI Disk Array Controllers (EISA/ISA/PCI)
1016 * Byte offset into the SCB Array and an optional bit to allow auto1281 field ARRDONE 0x40 /* SCB Array prefetch done */
2894 * CMC SCB Array Count
790 tristate "Windows-compatible SoC Button Array"