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Searched refs:BIT18 (Results 1 – 11 of 11) sorted by relevance

/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h626 #define RRSR_MCS6 BIT18
786 #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrup 1 */
834 #define PHIMR_BCNDOK2 BIT18
860 #define PHIMR_BCNDOK6 BIT18
885 #define UHIMR_BCNDOK2 BIT18
911 #define UHIMR_BCNDOK6 BIT18
969 #define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrup 5 */
1033 #define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */
1577 #define SDIO_HIMR_CPWM1_MSK BIT18
1603 #define SDIO_HISR_CPWM1 BIT18
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Drtl8723b_spec.h238 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */
Dosdep_service.h39 #define BIT18 0x00040000 macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h131 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
142 #define RCR_ADF BIT18
379 #define RRSR_MCS6 BIT18
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h49 #define BIT18 0x00040000 macro
/drivers/staging/rtl8192e/
Drtl819x_Qos.h28 #define BIT18 0x00040000 macro
/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h420 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */
Dhal_com.c1721 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
/drivers/scsi/
Ddc395x.h58 #define BIT18 0x00040000 macro
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h376 #define RRSR_MCS6 BIT18
/drivers/scsi/lpfc/
Dlpfc_hw4.h732 #define LPFC_SLI4_INTR18 BIT18