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Searched refs:BIT8 (Results 1 – 20 of 20) sorted by relevance

/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h616 #define RRSR_24M BIT8
796 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
812 #define IMR_CPWM BIT8
844 #define PHIMR_CPWM BIT8
867 #define PHIMR_RXFOVW BIT8
895 #define UHIMR_CPWM BIT8
920 #define UHIMR_RXFOVW BIT8
949 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
978 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
1043 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
Drtl8723b_spec.h218 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
247 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
Dosdep_service.h29 #define BIT8 0x00000100 macro
Drtw_mlme_ext.h52 #define DYNAMIC_BB_PWR_TRAIN BIT8 /* ODM_BB_PWR_TRAIN */
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h220 #define IMR_HIGHDOK BIT8
239 #define TPPoll_HCCAQ BIT8
369 #define RRSR_24M BIT8
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h39 #define BIT8 0x00000100 macro
Dhalbtcoutsrc.h100 #define ALGO_TRACE_SW_DETAIL BIT8
/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h400 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
429 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
Dodm_debug.h69 #define ODM_COMP_PWR_TRAIN BIT8
Drtl8723b_phycfg.c167 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
169 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
691 u2tmp = RegRfMod_BW | BIT8; in phy_SetRegBW_8723B()
Dodm.h427 ODM_BB_PWR_TRAIN = BIT8,
453 ODM_RTL8723B = BIT8,
536 ODM_WIFI_DISPLAY = BIT8,
DHalBtcOutSrc.h101 #define ALGO_TRACE_SW_DETAIL BIT8
Dodm_DIG.c24 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h18 #define BIT8 0x00000100 macro
/drivers/tty/
Dsynclink.c501 #define RXSTATUS_SHORT_FRAME BIT8
502 #define RXSTATUS_CODE_VIOLATION BIT8
563 #define MISCSTATUS_DSR BIT8
586 #define SICR_DSR_INACTIVE BIT8
587 #define SICR_DSR (BIT9|BIT8)
1639 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); in mgsl_isr_transmit_dma()
4675 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4677 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4838 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
4842 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
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Dsynclink_gt.c392 #define IRQ_RXOVER BIT8
2293 if (gsr & (BIT8 << i)) in slgt_interrupt()
4073 val |= BIT8; in async_mode()
4113 val |= BIT8; in async_mode()
4162 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()
4235 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4308 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4951 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
/drivers/scsi/
Ddc395x.h68 #define BIT8 0x00000100 macro
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h366 #define RRSR_24M BIT8
/drivers/scsi/lpfc/
Dlpfc_hw4.h722 #define LPFC_SLI4_INTR8 BIT8
/drivers/char/pcmcia/
Dsynclink_cs.c297 #define IRQ_TXFIFO BIT8 // transmit pool ready