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Searched refs:BLT_RING_BASE (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dmmio_context.c69 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
70 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
71 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
72 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
73 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
121 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
122 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
123 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
124 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
125 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
Dhandlers.c1912 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
3367 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/drivers/gpu/drm/i915/
Di915_cmd_parser.c634 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
667 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
674 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
675 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
Dintel_uncore.c952 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
960 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
974 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
Di915_reg.h2507 #define BLT_RING_BASE 0x22000 macro
2522 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2523 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2524 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
/drivers/gpu/drm/i915/gt/
Dintel_engine_cs.c86 { .gen = 6, .base = BLT_RING_BASE }