Searched refs:CACHE_MODE_1 (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| D | intel_workarounds.c | 286 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); in gen8_ctx_workarounds_init()
372 WA_SET_BIT_MASKED(CACHE_MODE_1, in gen9_ctx_workarounds_init()
872 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); in ivb_gt_workarounds_init()
923 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); in vlv_gt_workarounds_init()
966 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); in hsw_gt_workarounds_init()
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| D | gen7_renderclear.c | 404 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
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| /drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 62 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
94 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
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| D | handlers.c | 1999 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
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| /drivers/gpu/drm/i915/ |
| D | i915_reg.h | 3028 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ macro
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