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Searched refs:CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h980 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL macro
Dgfx_7_2_sh_mask.h9331 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f macro
Dgfx_8_0_sh_mask.h11055 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f macro
Dgfx_8_1_sh_mask.h11453 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h23928 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK … macro
Dgc_9_1_sh_mask.h25219 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK … macro
Dgc_9_2_1_sh_mask.h25350 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK … macro
Dgc_10_1_0_sh_mask.h35306 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK … macro