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Searched refs:CLK_BASE__INST0_SEG1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h184 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
Dnavi12_ip_offset.h238 #define CLK_BASE__INST0_SEG1 0x02401800 macro
Dvega20_ip_offset.h211 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
Dnavi14_ip_offset.h238 #define CLK_BASE__INST0_SEG1 0x02401800 macro
Dsienna_cichlid_ip_offset.h245 #define CLK_BASE__INST0_SEG1 0x02401800 macro
Dvega10_ip_offset.h1206 #define CLK_BASE__INST0_SEG1 0 macro
Drenoir_ip_offset.h320 #define CLK_BASE__INST0_SEG1 0x00016E00 macro
Darct_ip_offset.h303 #define CLK_BASE__INST0_SEG1 0x00016C00 macro