Searched refs:CLK_SDMMC0 (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/zte/ |
| D | clk-zx296702.c | 48 #define CLK_SDMMC0 (lsp1crpm_base + 0x2c) macro
708 ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1); in zx296702_lsp1_clocks_init()
710 zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4); in zx296702_lsp1_clocks_init()
712 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1); in zx296702_lsp1_clocks_init()
714 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0); in zx296702_lsp1_clocks_init()
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| /drivers/clk/samsung/ |
| D | clk-exynos5250.c | 561 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
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| D | clk-exynos3250.c | 645 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
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| D | clk-exynos4.c | 839 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
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