Searched refs:CLK_UART0 (Results 1 – 13 of 13) sorted by relevance
| /drivers/clk/zte/ |
| D | clk-zx296702.c | 46 #define CLK_UART0 (lsp1crpm_base + 0x20) macro
688 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1); in zx296702_lsp1_clocks_init()
692 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31); in zx296702_lsp1_clocks_init()
694 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0); in zx296702_lsp1_clocks_init()
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| /drivers/clk/samsung/ |
| D | clk-exynos5410.c | 197 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
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| D | clk-s5pv210.c | 576 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
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| D | clk-exynos5250.c | 573 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
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| D | clk-exynos3250.c | 665 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
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| D | clk-exynos4.c | 848 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
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| D | clk-exynos5420.c | 1051 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
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| /drivers/clk/pistachio/ |
| D | clk-pistachio.c | 35 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
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| /drivers/clk/actions/ |
| D | owl-s500.c | 476 [CLK_UART0] = &uart0_clk.common.hw,
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| D | owl-s700.c | 526 [CLK_UART0] = &clk_uart0.common.hw,
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| D | owl-s900.c | 676 [CLK_UART0] = &uart0_clk.common.hw,
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| /drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 302 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
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| /drivers/clk/sprd/ |
| D | sc9860-clk.c | 467 [CLK_UART0] = &uart0_clk.common.hw,
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