Searched refs:CLK_UART1 (Results 1 – 13 of 13) sorted by relevance
| /drivers/clk/zte/ |
| D | clk-zx296702.c | 47 #define CLK_UART1 (lsp1crpm_base + 0x24) macro
699 ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1); in zx296702_lsp1_clocks_init()
701 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1); in zx296702_lsp1_clocks_init()
703 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0); in zx296702_lsp1_clocks_init()
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| /drivers/clk/samsung/ |
| D | clk-exynos5410.c | 198 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-s5pv210.c | 575 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
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| D | clk-exynos5250.c | 574 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-exynos3250.c | 664 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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| D | clk-exynos4.c | 850 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
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| D | clk-exynos5420.c | 1053 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
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| /drivers/clk/pistachio/ |
| D | clk-pistachio.c | 36 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
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| /drivers/clk/actions/ |
| D | owl-s500.c | 477 [CLK_UART1] = &uart1_clk.common.hw,
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| D | owl-s700.c | 527 [CLK_UART1] = &clk_uart1.common.hw,
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| D | owl-s900.c | 677 [CLK_UART1] = &uart1_clk.common.hw,
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| /drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 303 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
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| /drivers/clk/sprd/ |
| D | sc9860-clk.c | 468 [CLK_UART1] = &uart1_clk.common.hw,
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