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Searched refs:CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h2506 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 macro
Dgfx_8_1_sh_mask.h3028 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11943 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
Dgc_9_1_sh_mask.h13373 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
Dgc_9_2_1_sh_mask.h13151 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
Dgc_10_3_0_sh_mask.h34682 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
Dgc_10_1_0_sh_mask.h39453 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro