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Searched refs:CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h3251 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 macro
Dgfx_8_0_sh_mask.h3871 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 macro
Dgfx_8_1_sh_mask.h4393 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12756 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK … macro
Dgc_9_1_sh_mask.h14060 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK … macro
Dgc_9_2_1_sh_mask.h13925 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK … macro
Dgc_10_3_0_sh_mask.h18247 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK … macro
Dgc_10_1_0_sh_mask.h20038 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK … macro