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Searched refs:CP_HPD_STATUS0__QUEUE_STATE_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h3877 #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f macro
Dgfx_8_1_sh_mask.h4399 #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12768 #define CP_HPD_STATUS0__QUEUE_STATE_MASK … macro
Dgc_9_1_sh_mask.h14072 #define CP_HPD_STATUS0__QUEUE_STATE_MASK … macro
Dgc_9_2_1_sh_mask.h13937 #define CP_HPD_STATUS0__QUEUE_STATE_MASK … macro
Dgc_10_3_0_sh_mask.h18262 #define CP_HPD_STATUS0__QUEUE_STATE_MASK … macro
Dgc_10_1_0_sh_mask.h20053 #define CP_HPD_STATUS0__QUEUE_STATE_MASK … macro