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Searched refs:CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h4072 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 macro
Dgfx_8_1_sh_mask.h4594 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h13029 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT … macro
Dgc_9_1_sh_mask.h14333 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT … macro
Dgc_9_2_1_sh_mask.h14198 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT … macro
Dgc_10_3_0_sh_mask.h18536 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT … macro
Dgc_10_1_0_sh_mask.h20329 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT … macro