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Searched refs:CP_HQD_IQ_RPTR__OFFSET_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h3401 #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f macro
Dgfx_8_0_sh_mask.h4023 #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f macro
Dgfx_8_1_sh_mask.h4545 #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12971 #define CP_HQD_IQ_RPTR__OFFSET_MASK … macro
Dgc_9_1_sh_mask.h14275 #define CP_HQD_IQ_RPTR__OFFSET_MASK … macro
Dgc_9_2_1_sh_mask.h14140 #define CP_HQD_IQ_RPTR__OFFSET_MASK … macro
Dgc_10_3_0_sh_mask.h18474 #define CP_HQD_IQ_RPTR__OFFSET_MASK … macro
Dgc_10_1_0_sh_mask.h20267 #define CP_HQD_IQ_RPTR__OFFSET_MASK … macro