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Searched refs:CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h4009 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 macro
Dgfx_8_1_sh_mask.h4531 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12961 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK … macro
Dgc_9_1_sh_mask.h14265 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK … macro
Dgc_9_2_1_sh_mask.h14130 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK … macro
Dgc_10_3_0_sh_mask.h18463 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK … macro
Dgc_10_1_0_sh_mask.h20256 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK … macro