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Searched refs:CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h3967 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
Dgfx_8_1_sh_mask.h4489 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12914 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
Dgc_9_1_sh_mask.h14218 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
Dgc_9_2_1_sh_mask.h14083 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
Dgc_10_3_0_sh_mask.h18409 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
Dgc_10_1_0_sh_mask.h20202 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro