Home
last modified time | relevance | path

Searched refs:CP_ME_CNTL__ME_HALT_MASK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2436 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v7_0_cp_gfx_enable()
4682 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
Dgfx_v6_0.c1957 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2566 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L macro
Dgfx_7_2_sh_mask.h3053 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
Dgfx_8_0_sh_mask.h3667 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
Dgfx_8_1_sh_mask.h4189 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h1177 #define CP_ME_CNTL__ME_HALT_MASK … macro
Dgc_9_1_sh_mask.h1076 #define CP_ME_CNTL__ME_HALT_MASK … macro
Dgc_9_2_1_sh_mask.h1043 #define CP_ME_CNTL__ME_HALT_MASK … macro
Dgc_10_3_0_sh_mask.h6927 #define CP_ME_CNTL__ME_HALT_MASK … macro
Dgc_10_1_0_sh_mask.h6665 #define CP_ME_CNTL__ME_HALT_MASK … macro