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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h1877 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 macro
Dgfx_8_1_sh_mask.h2399 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11204 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK … macro
Dgc_9_1_sh_mask.h12685 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK … macro
Dgc_9_2_1_sh_mask.h12483 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK … macro
Dgc_10_3_0_sh_mask.h16503 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK … macro
Dgc_10_1_0_sh_mask.h18167 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK … macro