Home
last modified time | relevance | path

Searched refs:CSR2 (Results 1 – 12 of 12) sorted by relevance

/drivers/media/pci/dt3155/
Ddt3155.h48 #define CSR2 0x10 macro
Ddt3155.c172 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); in dt3155_start_streaming()
183 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2); in dt3155_stop_streaming()
/drivers/net/ethernet/amd/
Dariadne.h64 #define CSR2 0x0200 /* - IADR[23:16] */ macro
Dsun3lance.c205 #define CSR2 2 /* init block addr (high) */ macro
504 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16; in lance_init_ring()
Datarilance.c305 #define CSR2 2 /* init block addr (high) */ macro
653 REGA( CSR2 ) = 0; in lance_open()
Dni65.c152 #define CSR2 0x02 macro
588 writereg(pib >> 16,CSR2); in ni65_init_lance()
/drivers/net/ethernet/dec/tulip/
Dtulip.h108 CSR2 = 0x10, enumerator
Dxircom_cb.c50 #define CSR2 0x10 macro
553 xw32(CSR2, 0); in trigger_receive()
Dinterrupt.c97 iowrite32(0x01, tp->base_addr + CSR2); in tulip_refill_rx()
Dtulip_core.c483 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */ in tulip_up()
/drivers/net/wireless/ralink/rt2x00/
Drt2400pci.h71 #define CSR2 0x0008 macro
Drt2500pci.h82 #define CSR2 0x0008 macro