1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 *
19 */
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pm_qos.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <linux/dmi.h>
27 #include <linux/interrupt.h>
28
29 #include <asm/iosf_mbi.h>
30
31 #include "../../include/linux/atomisp_gmin_platform.h"
32
33 #include "atomisp_cmd.h"
34 #include "atomisp_common.h"
35 #include "atomisp_fops.h"
36 #include "atomisp_file.h"
37 #include "atomisp_ioctl.h"
38 #include "atomisp_internal.h"
39 #include "atomisp_acc.h"
40 #include "atomisp-regs.h"
41 #include "atomisp_dfs_tables.h"
42 #include "atomisp_drvfs.h"
43 #include "hmm/hmm.h"
44 #include "atomisp_trace_event.h"
45
46 #include "sh_css_firmware.h"
47
48 #include "device_access.h"
49
50 /* Timeouts to wait for all subdevs to be registered */
51 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
52 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
53
54 /* G-Min addition: pull this in from intel_mid_pm.h */
55 #define CSTATE_EXIT_LATENCY_C1 1
56
57 static uint skip_fwload;
58 module_param(skip_fwload, uint, 0644);
59 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load");
60
61 /* set reserved memory pool size in page */
62 static unsigned int repool_pgnr = 32768;
63 module_param(repool_pgnr, uint, 0644);
64 MODULE_PARM_DESC(repool_pgnr,
65 "Set the reserved memory pool size in page (default:32768)");
66
67 /* set dynamic memory pool size in page */
68 unsigned int dypool_pgnr = UINT_MAX;
69 module_param(dypool_pgnr, uint, 0644);
70 MODULE_PARM_DESC(dypool_pgnr,
71 "Set the dynamic memory pool size in page (default: unlimited)");
72
73 bool dypool_enable = true;
74 module_param(dypool_enable, bool, 0644);
75 MODULE_PARM_DESC(dypool_enable,
76 "dynamic memory pool enable/disable (default:enabled)");
77
78 /* memory optimization: deferred firmware loading */
79 bool defer_fw_load;
80 module_param(defer_fw_load, bool, 0644);
81 MODULE_PARM_DESC(defer_fw_load,
82 "Defer FW loading until device is opened (default:disable)");
83
84 /* cross componnet debug message flag */
85 int dbg_level;
86 module_param(dbg_level, int, 0644);
87 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
88
89 /* log function switch */
90 int dbg_func = 2;
91 module_param(dbg_func, int, 0644);
92 MODULE_PARM_DESC(dbg_func,
93 "log function switch non/trace_printk/printk (default:printk)");
94
95 int mipicsi_flag;
96 module_param(mipicsi_flag, int, 0644);
97 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
98
99 static char firmware_name[256];
100 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
101 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
102
103 /*set to 16x16 since this is the amount of lines and pixels the sensor
104 exports extra. If these are kept at the 10x8 that they were on, in yuv
105 downscaling modes incorrect resolutions where requested to the sensor
106 driver with strange outcomes as a result. The proper way tot do this
107 would be to have a list of tables the specify the sensor res, mipi rec,
108 output res, and isp output res. however since we do not have this yet,
109 the chosen solution is the next best thing. */
110 int pad_w = 16;
111 module_param(pad_w, int, 0644);
112 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
113
114 int pad_h = 16;
115 module_param(pad_h, int, 0644);
116 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
117
118 /*
119 * FIXME: this is a hack to make easier to support ISP2401 variant.
120 * As a given system will either be ISP2401 or not, we can just use
121 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
122 *
123 * Once this driver gets into a better shape, however, the best would
124 * be to replace this to something stored inside atomisp allocated
125 * structures.
126 */
127
128 struct device *atomisp_dev;
129
130 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
131 {
132 .width = ISP_FREQ_RULE_ANY,
133 .height = ISP_FREQ_RULE_ANY,
134 .fps = ISP_FREQ_RULE_ANY,
135 .isp_freq = ISP_FREQ_400MHZ,
136 .run_mode = ATOMISP_RUN_MODE_VIDEO,
137 },
138 {
139 .width = ISP_FREQ_RULE_ANY,
140 .height = ISP_FREQ_RULE_ANY,
141 .fps = ISP_FREQ_RULE_ANY,
142 .isp_freq = ISP_FREQ_400MHZ,
143 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
144 },
145 {
146 .width = ISP_FREQ_RULE_ANY,
147 .height = ISP_FREQ_RULE_ANY,
148 .fps = ISP_FREQ_RULE_ANY,
149 .isp_freq = ISP_FREQ_400MHZ,
150 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
151 },
152 {
153 .width = ISP_FREQ_RULE_ANY,
154 .height = ISP_FREQ_RULE_ANY,
155 .fps = ISP_FREQ_RULE_ANY,
156 .isp_freq = ISP_FREQ_400MHZ,
157 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
158 },
159 {
160 .width = ISP_FREQ_RULE_ANY,
161 .height = ISP_FREQ_RULE_ANY,
162 .fps = ISP_FREQ_RULE_ANY,
163 .isp_freq = ISP_FREQ_457MHZ,
164 .run_mode = ATOMISP_RUN_MODE_SDV,
165 },
166 };
167
168 /* Merrifield and Moorefield DFS rules */
169 static const struct atomisp_dfs_config dfs_config_merr = {
170 .lowest_freq = ISP_FREQ_200MHZ,
171 .max_freq_at_vmin = ISP_FREQ_400MHZ,
172 .highest_freq = ISP_FREQ_457MHZ,
173 .dfs_table = dfs_rules_merr,
174 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
175 };
176
177 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
178 {
179 .width = ISP_FREQ_RULE_ANY,
180 .height = ISP_FREQ_RULE_ANY,
181 .fps = ISP_FREQ_RULE_ANY,
182 .isp_freq = ISP_FREQ_400MHZ,
183 .run_mode = ATOMISP_RUN_MODE_VIDEO,
184 },
185 {
186 .width = ISP_FREQ_RULE_ANY,
187 .height = ISP_FREQ_RULE_ANY,
188 .fps = ISP_FREQ_RULE_ANY,
189 .isp_freq = ISP_FREQ_400MHZ,
190 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
191 },
192 {
193 .width = ISP_FREQ_RULE_ANY,
194 .height = ISP_FREQ_RULE_ANY,
195 .fps = ISP_FREQ_RULE_ANY,
196 .isp_freq = ISP_FREQ_400MHZ,
197 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
198 },
199 {
200 .width = ISP_FREQ_RULE_ANY,
201 .height = ISP_FREQ_RULE_ANY,
202 .fps = ISP_FREQ_RULE_ANY,
203 .isp_freq = ISP_FREQ_400MHZ,
204 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
205 },
206 {
207 .width = ISP_FREQ_RULE_ANY,
208 .height = ISP_FREQ_RULE_ANY,
209 .fps = ISP_FREQ_RULE_ANY,
210 .isp_freq = ISP_FREQ_400MHZ,
211 .run_mode = ATOMISP_RUN_MODE_SDV,
212 },
213 };
214
215 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
216 .lowest_freq = ISP_FREQ_200MHZ,
217 .max_freq_at_vmin = ISP_FREQ_400MHZ,
218 .highest_freq = ISP_FREQ_400MHZ,
219 .dfs_table = dfs_rules_merr_1179,
220 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
221 };
222
223 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
224 {
225 .width = 1920,
226 .height = 1080,
227 .fps = 30,
228 .isp_freq = ISP_FREQ_266MHZ,
229 .run_mode = ATOMISP_RUN_MODE_VIDEO,
230 },
231 {
232 .width = 1080,
233 .height = 1920,
234 .fps = 30,
235 .isp_freq = ISP_FREQ_266MHZ,
236 .run_mode = ATOMISP_RUN_MODE_VIDEO,
237 },
238 {
239 .width = 1920,
240 .height = 1080,
241 .fps = 45,
242 .isp_freq = ISP_FREQ_320MHZ,
243 .run_mode = ATOMISP_RUN_MODE_VIDEO,
244 },
245 {
246 .width = 1080,
247 .height = 1920,
248 .fps = 45,
249 .isp_freq = ISP_FREQ_320MHZ,
250 .run_mode = ATOMISP_RUN_MODE_VIDEO,
251 },
252 {
253 .width = ISP_FREQ_RULE_ANY,
254 .height = ISP_FREQ_RULE_ANY,
255 .fps = 60,
256 .isp_freq = ISP_FREQ_356MHZ,
257 .run_mode = ATOMISP_RUN_MODE_VIDEO,
258 },
259 {
260 .width = ISP_FREQ_RULE_ANY,
261 .height = ISP_FREQ_RULE_ANY,
262 .fps = ISP_FREQ_RULE_ANY,
263 .isp_freq = ISP_FREQ_200MHZ,
264 .run_mode = ATOMISP_RUN_MODE_VIDEO,
265 },
266 {
267 .width = ISP_FREQ_RULE_ANY,
268 .height = ISP_FREQ_RULE_ANY,
269 .fps = ISP_FREQ_RULE_ANY,
270 .isp_freq = ISP_FREQ_400MHZ,
271 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
272 },
273 {
274 .width = ISP_FREQ_RULE_ANY,
275 .height = ISP_FREQ_RULE_ANY,
276 .fps = ISP_FREQ_RULE_ANY,
277 .isp_freq = ISP_FREQ_400MHZ,
278 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
279 },
280 {
281 .width = ISP_FREQ_RULE_ANY,
282 .height = ISP_FREQ_RULE_ANY,
283 .fps = ISP_FREQ_RULE_ANY,
284 .isp_freq = ISP_FREQ_200MHZ,
285 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
286 },
287 {
288 .width = ISP_FREQ_RULE_ANY,
289 .height = ISP_FREQ_RULE_ANY,
290 .fps = ISP_FREQ_RULE_ANY,
291 .isp_freq = ISP_FREQ_400MHZ,
292 .run_mode = ATOMISP_RUN_MODE_SDV,
293 },
294 };
295
296 static struct atomisp_dfs_config dfs_config_merr_117a = {
297 .lowest_freq = ISP_FREQ_200MHZ,
298 .max_freq_at_vmin = ISP_FREQ_200MHZ,
299 .highest_freq = ISP_FREQ_400MHZ,
300 .dfs_table = dfs_rules_merr_117a,
301 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
302 };
303
304 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
305 {
306 .width = ISP_FREQ_RULE_ANY,
307 .height = ISP_FREQ_RULE_ANY,
308 .fps = ISP_FREQ_RULE_ANY,
309 .isp_freq = ISP_FREQ_400MHZ,
310 .run_mode = ATOMISP_RUN_MODE_VIDEO,
311 },
312 {
313 .width = ISP_FREQ_RULE_ANY,
314 .height = ISP_FREQ_RULE_ANY,
315 .fps = ISP_FREQ_RULE_ANY,
316 .isp_freq = ISP_FREQ_400MHZ,
317 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
318 },
319 {
320 .width = ISP_FREQ_RULE_ANY,
321 .height = ISP_FREQ_RULE_ANY,
322 .fps = ISP_FREQ_RULE_ANY,
323 .isp_freq = ISP_FREQ_400MHZ,
324 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
325 },
326 {
327 .width = ISP_FREQ_RULE_ANY,
328 .height = ISP_FREQ_RULE_ANY,
329 .fps = ISP_FREQ_RULE_ANY,
330 .isp_freq = ISP_FREQ_400MHZ,
331 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
332 },
333 {
334 .width = ISP_FREQ_RULE_ANY,
335 .height = ISP_FREQ_RULE_ANY,
336 .fps = ISP_FREQ_RULE_ANY,
337 .isp_freq = ISP_FREQ_400MHZ,
338 .run_mode = ATOMISP_RUN_MODE_SDV,
339 },
340 };
341
342 static const struct atomisp_dfs_config dfs_config_byt = {
343 .lowest_freq = ISP_FREQ_200MHZ,
344 .max_freq_at_vmin = ISP_FREQ_400MHZ,
345 .highest_freq = ISP_FREQ_400MHZ,
346 .dfs_table = dfs_rules_byt,
347 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
348 };
349
350 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
351 {
352 .width = ISP_FREQ_RULE_ANY,
353 .height = ISP_FREQ_RULE_ANY,
354 .fps = ISP_FREQ_RULE_ANY,
355 .isp_freq = ISP_FREQ_320MHZ,
356 .run_mode = ATOMISP_RUN_MODE_VIDEO,
357 },
358 {
359 .width = ISP_FREQ_RULE_ANY,
360 .height = ISP_FREQ_RULE_ANY,
361 .fps = ISP_FREQ_RULE_ANY,
362 .isp_freq = ISP_FREQ_356MHZ,
363 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
364 },
365 {
366 .width = ISP_FREQ_RULE_ANY,
367 .height = ISP_FREQ_RULE_ANY,
368 .fps = ISP_FREQ_RULE_ANY,
369 .isp_freq = ISP_FREQ_320MHZ,
370 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
371 },
372 {
373 .width = ISP_FREQ_RULE_ANY,
374 .height = ISP_FREQ_RULE_ANY,
375 .fps = ISP_FREQ_RULE_ANY,
376 .isp_freq = ISP_FREQ_320MHZ,
377 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
378 },
379 {
380 .width = 1280,
381 .height = 720,
382 .fps = ISP_FREQ_RULE_ANY,
383 .isp_freq = ISP_FREQ_320MHZ,
384 .run_mode = ATOMISP_RUN_MODE_SDV,
385 },
386 {
387 .width = ISP_FREQ_RULE_ANY,
388 .height = ISP_FREQ_RULE_ANY,
389 .fps = ISP_FREQ_RULE_ANY,
390 .isp_freq = ISP_FREQ_356MHZ,
391 .run_mode = ATOMISP_RUN_MODE_SDV,
392 },
393 };
394
395 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
396 {
397 .width = ISP_FREQ_RULE_ANY,
398 .height = ISP_FREQ_RULE_ANY,
399 .fps = ISP_FREQ_RULE_ANY,
400 .isp_freq = ISP_FREQ_356MHZ,
401 .run_mode = ATOMISP_RUN_MODE_VIDEO,
402 },
403 {
404 .width = ISP_FREQ_RULE_ANY,
405 .height = ISP_FREQ_RULE_ANY,
406 .fps = ISP_FREQ_RULE_ANY,
407 .isp_freq = ISP_FREQ_356MHZ,
408 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
409 },
410 {
411 .width = ISP_FREQ_RULE_ANY,
412 .height = ISP_FREQ_RULE_ANY,
413 .fps = ISP_FREQ_RULE_ANY,
414 .isp_freq = ISP_FREQ_320MHZ,
415 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
416 },
417 {
418 .width = ISP_FREQ_RULE_ANY,
419 .height = ISP_FREQ_RULE_ANY,
420 .fps = ISP_FREQ_RULE_ANY,
421 .isp_freq = ISP_FREQ_320MHZ,
422 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
423 },
424 {
425 .width = ISP_FREQ_RULE_ANY,
426 .height = ISP_FREQ_RULE_ANY,
427 .fps = ISP_FREQ_RULE_ANY,
428 .isp_freq = ISP_FREQ_356MHZ,
429 .run_mode = ATOMISP_RUN_MODE_SDV,
430 },
431 };
432
433 static const struct atomisp_dfs_config dfs_config_cht = {
434 .lowest_freq = ISP_FREQ_100MHZ,
435 .max_freq_at_vmin = ISP_FREQ_356MHZ,
436 .highest_freq = ISP_FREQ_356MHZ,
437 .dfs_table = dfs_rules_cht,
438 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
439 };
440
441 /* This one should be visible also by atomisp_cmd.c */
442 const struct atomisp_dfs_config dfs_config_cht_soc = {
443 .lowest_freq = ISP_FREQ_100MHZ,
444 .max_freq_at_vmin = ISP_FREQ_356MHZ,
445 .highest_freq = ISP_FREQ_356MHZ,
446 .dfs_table = dfs_rules_cht_soc,
447 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
448 };
449
atomisp_video_init(struct atomisp_video_pipe * video,const char * name,unsigned int run_mode)450 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name,
451 unsigned int run_mode)
452 {
453 int ret;
454 const char *direction;
455
456 switch (video->type) {
457 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
458 direction = "output";
459 video->pad.flags = MEDIA_PAD_FL_SINK;
460 video->vdev.fops = &atomisp_fops;
461 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
462 break;
463 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
464 direction = "input";
465 video->pad.flags = MEDIA_PAD_FL_SOURCE;
466 video->vdev.fops = &atomisp_file_fops;
467 video->vdev.ioctl_ops = &atomisp_file_ioctl_ops;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
474 if (ret < 0)
475 return ret;
476
477 /* Initialize the video device. */
478 snprintf(video->vdev.name, sizeof(video->vdev.name),
479 "ATOMISP ISP %s %s", name, direction);
480 video->vdev.release = video_device_release_empty;
481 video_set_drvdata(&video->vdev, video->isp);
482 video->default_run_mode = run_mode;
483
484 return 0;
485 }
486
atomisp_acc_init(struct atomisp_acc_pipe * video,const char * name)487 void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name)
488 {
489 video->vdev.fops = &atomisp_fops;
490 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
491
492 /* Initialize the video device. */
493 snprintf(video->vdev.name, sizeof(video->vdev.name),
494 "ATOMISP ISP %s", name);
495 video->vdev.release = video_device_release_empty;
496 video_set_drvdata(&video->vdev, video->isp);
497 }
498
atomisp_video_unregister(struct atomisp_video_pipe * video)499 void atomisp_video_unregister(struct atomisp_video_pipe *video)
500 {
501 if (video_is_registered(&video->vdev)) {
502 media_entity_cleanup(&video->vdev.entity);
503 video_unregister_device(&video->vdev);
504 }
505 }
506
atomisp_acc_unregister(struct atomisp_acc_pipe * video)507 void atomisp_acc_unregister(struct atomisp_acc_pipe *video)
508 {
509 if (video_is_registered(&video->vdev))
510 video_unregister_device(&video->vdev);
511 }
512
atomisp_save_iunit_reg(struct atomisp_device * isp)513 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
514 {
515 struct pci_dev *pdev = to_pci_dev(isp->dev);
516
517 dev_dbg(isp->dev, "%s\n", __func__);
518
519 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
520 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
521 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
522 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
523 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
524 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
525 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
526
527 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
528 /* Ensure read/write combining is enabled. */
529 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
530 isp->saved_regs.i_control |=
531 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
532 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
533 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
534 &isp->saved_regs.csi_access_viol);
535 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
536 &isp->saved_regs.csi_rcomp_config);
537 /*
538 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
539 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
540 * and sensor sending "continuous clock".
541 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
542 * is missed, and IUNIT can hang.
543 * For both issues, setting this bit is a workaround.
544 */
545 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
546 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
547 &isp->saved_regs.csi_afe_dly);
548 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
549 &isp->saved_regs.csi_control);
550 if (isp->media_dev.hw_revision >=
551 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
552 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
553 /*
554 * On CHT CSI_READY bit should be enabled before stream on
555 */
556 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
557 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
558 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
559 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
560 &isp->saved_regs.csi_afe_rcomp_config);
561 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
562 &isp->saved_regs.csi_afe_hs_control);
563 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
564 &isp->saved_regs.csi_deadline_control);
565 return 0;
566 }
567
atomisp_restore_iunit_reg(struct atomisp_device * isp)568 static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp)
569 {
570 struct pci_dev *pdev = to_pci_dev(isp->dev);
571
572 dev_dbg(isp->dev, "%s\n", __func__);
573
574 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
575 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
576 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
577 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
578 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
579 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
580 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
581 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
582
583 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
584 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
585 isp->saved_regs.csi_access_viol);
586 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
587 isp->saved_regs.csi_rcomp_config);
588 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
589 isp->saved_regs.csi_afe_dly);
590 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
591 isp->saved_regs.csi_control);
592 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
593 isp->saved_regs.csi_afe_rcomp_config);
594 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
595 isp->saved_regs.csi_afe_hs_control);
596 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
597 isp->saved_regs.csi_deadline_control);
598
599 /*
600 * for MRFLD, Software/firmware needs to write a 1 to bit0
601 * of the register at CSI_RECEIVER_SELECTION_REG to enable
602 * SH CSI backend write 0 will enable Arasan CSI backend,
603 * which has bugs(like sighting:4567697 and 4567699) and
604 * will be removed in B0
605 */
606 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
607 return 0;
608 }
609
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)610 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
611 {
612 struct pci_dev *pdev = to_pci_dev(isp->dev);
613 u32 irq;
614 unsigned long flags;
615
616 spin_lock_irqsave(&isp->lock, flags);
617 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
618 spin_unlock_irqrestore(&isp->lock, flags);
619 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__);
620 return 0;
621 }
622 /*
623 * MRFLD HAS requirement: cannot power off i-unit if
624 * ISP has IRQ not serviced.
625 * So, here we need to check if there is any pending
626 * IRQ, if so, waiting for it to be served
627 */
628 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
629 irq = irq & 1 << INTR_IIR;
630 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
631
632 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
633 if (!(irq & (1 << INTR_IIR)))
634 goto done;
635
636 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
637 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
638 if (irq != 0) {
639 dev_err(isp->dev,
640 "%s: fail to clear isp interrupt status reg=0x%x\n",
641 __func__, irq);
642 spin_unlock_irqrestore(&isp->lock, flags);
643 return -EAGAIN;
644 } else {
645 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
646 irq = irq & 1 << INTR_IIR;
647 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
648
649 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
650 if (!(irq & (1 << INTR_IIR))) {
651 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
652 goto done;
653 }
654 dev_err(isp->dev,
655 "%s: error in iunit interrupt. status reg=0x%x\n",
656 __func__, irq);
657 spin_unlock_irqrestore(&isp->lock, flags);
658 return -EAGAIN;
659 }
660 done:
661 /*
662 * MRFLD WORKAROUND:
663 * before powering off IUNIT, clear the pending interrupts
664 * and disable the interrupt. driver should avoid writing 0
665 * to IIR. It could block subsequent interrupt messages.
666 * HW sighting:4568410.
667 */
668 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
669 irq &= ~(1 << INTR_IER);
670 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
671
672 atomisp_msi_irq_uninit(isp);
673 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
674 spin_unlock_irqrestore(&isp->lock, flags);
675
676 return 0;
677 }
678
679 /*
680 * WA for DDR DVFS enable/disable
681 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
682 */
punit_ddr_dvfs_enable(bool enable)683 static void punit_ddr_dvfs_enable(bool enable)
684 {
685 int door_bell = 1 << 8;
686 int max_wait = 30;
687 int reg;
688
689 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
690 if (enable) {
691 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
692 } else {
693 reg |= (MRFLD_BIT1 | door_bell);
694 reg &= ~(MRFLD_BIT0);
695 }
696 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
697
698 /* Check Req_ACK to see freq status, wait until door_bell is cleared */
699 while ((reg & door_bell) && max_wait--) {
700 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
701 usleep_range(100, 500);
702 }
703
704 if (max_wait == -1)
705 pr_info("DDR DVFS, door bell is not cleared within 3ms\n");
706 }
707
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)708 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
709 {
710 unsigned long timeout;
711 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
712 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
713
714 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
715
716 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
717 if (IS_CHT && enable)
718 punit_ddr_dvfs_enable(false);
719
720 /*
721 * FIXME:WA for ECS28A, with this sleep, CTS
722 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort
723 * PASS, no impact on other platforms
724 */
725 if (IS_BYT && enable)
726 msleep(10);
727
728 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
729 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
730 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
731
732 /* WA:Enable DVFS */
733 if (IS_CHT && !enable)
734 punit_ddr_dvfs_enable(true);
735
736 /*
737 * There should be no IUNIT access while power-down is
738 * in progress. HW sighting: 4567865.
739 * Wait up to 50 ms for the IUNIT to shut down.
740 * And we do the same for power on.
741 */
742 timeout = jiffies + msecs_to_jiffies(50);
743 do {
744 u32 tmp;
745
746 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
747 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
748 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
749 if (tmp == val) {
750 trace_ipu_cstate(enable);
751 return 0;
752 }
753
754 if (time_after(jiffies, timeout))
755 break;
756
757 /* FIXME: experienced value for delay */
758 usleep_range(100, 150);
759 } while (1);
760
761 if (enable)
762 msleep(10);
763
764 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
765 return -EBUSY;
766 }
767
768 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */
atomisp_mrfld_power_down(struct atomisp_device * isp)769 int atomisp_mrfld_power_down(struct atomisp_device *isp)
770 {
771 return atomisp_mrfld_power(isp, false);
772 }
773
774 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */
atomisp_mrfld_power_up(struct atomisp_device * isp)775 int atomisp_mrfld_power_up(struct atomisp_device *isp)
776 {
777 return atomisp_mrfld_power(isp, true);
778 }
779
atomisp_runtime_suspend(struct device * dev)780 int atomisp_runtime_suspend(struct device *dev)
781 {
782 struct atomisp_device *isp = (struct atomisp_device *)
783 dev_get_drvdata(dev);
784 int ret;
785
786 ret = atomisp_mrfld_pre_power_down(isp);
787 if (ret)
788 return ret;
789
790 /*Turn off the ISP d-phy*/
791 ret = atomisp_ospm_dphy_down(isp);
792 if (ret)
793 return ret;
794 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
795 return atomisp_mrfld_power_down(isp);
796 }
797
atomisp_runtime_resume(struct device * dev)798 int atomisp_runtime_resume(struct device *dev)
799 {
800 struct atomisp_device *isp = (struct atomisp_device *)
801 dev_get_drvdata(dev);
802 int ret;
803
804 ret = atomisp_mrfld_power_up(isp);
805 if (ret)
806 return ret;
807
808 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
809 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
810 /*Turn on ISP d-phy */
811 ret = atomisp_ospm_dphy_up(isp);
812 if (ret) {
813 dev_err(isp->dev, "Failed to power up ISP!.\n");
814 return -EINVAL;
815 }
816 }
817
818 /*restore register values for iUnit and iUnitPHY registers*/
819 if (isp->saved_regs.pcicmdsts)
820 atomisp_restore_iunit_reg(isp);
821
822 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
823 return 0;
824 }
825
atomisp_suspend(struct device * dev)826 static int __maybe_unused atomisp_suspend(struct device *dev)
827 {
828 struct atomisp_device *isp = (struct atomisp_device *)
829 dev_get_drvdata(dev);
830 /* FIXME: only has one isp_subdev at present */
831 struct atomisp_sub_device *asd = &isp->asd[0];
832 unsigned long flags;
833 int ret;
834
835 /*
836 * FIXME: Suspend is not supported by sensors. Abort if any video
837 * node was opened.
838 */
839 if (atomisp_dev_users(isp))
840 return -EBUSY;
841
842 spin_lock_irqsave(&isp->lock, flags);
843 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
844 spin_unlock_irqrestore(&isp->lock, flags);
845 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
846 return -EINVAL;
847 }
848 spin_unlock_irqrestore(&isp->lock, flags);
849
850 ret = atomisp_mrfld_pre_power_down(isp);
851 if (ret)
852 return ret;
853
854 /*Turn off the ISP d-phy */
855 ret = atomisp_ospm_dphy_down(isp);
856 if (ret) {
857 dev_err(isp->dev, "fail to power off ISP\n");
858 return ret;
859 }
860 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
861 return atomisp_mrfld_power_down(isp);
862 }
863
atomisp_resume(struct device * dev)864 static int __maybe_unused atomisp_resume(struct device *dev)
865 {
866 struct atomisp_device *isp = (struct atomisp_device *)
867 dev_get_drvdata(dev);
868 int ret;
869
870 ret = atomisp_mrfld_power_up(isp);
871 if (ret)
872 return ret;
873
874 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
875
876 /*Turn on ISP d-phy */
877 ret = atomisp_ospm_dphy_up(isp);
878 if (ret) {
879 dev_err(isp->dev, "Failed to power up ISP!.\n");
880 return -EINVAL;
881 }
882
883 /*restore register values for iUnit and iUnitPHY registers*/
884 if (isp->saved_regs.pcicmdsts)
885 atomisp_restore_iunit_reg(isp);
886
887 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
888 return 0;
889 }
890
atomisp_csi_lane_config(struct atomisp_device * isp)891 int atomisp_csi_lane_config(struct atomisp_device *isp)
892 {
893 struct pci_dev *pdev = to_pci_dev(isp->dev);
894 static const struct {
895 u8 code;
896 u8 lanes[MRFLD_PORT_NUM];
897 } portconfigs[] = {
898 /* Tangier/Merrifield available lane configurations */
899 { 0x00, { 4, 1, 0 } }, /* 00000 */
900 { 0x01, { 3, 1, 0 } }, /* 00001 */
901 { 0x02, { 2, 1, 0 } }, /* 00010 */
902 { 0x03, { 1, 1, 0 } }, /* 00011 */
903 { 0x04, { 2, 1, 2 } }, /* 00100 */
904 { 0x08, { 3, 1, 1 } }, /* 01000 */
905 { 0x09, { 2, 1, 1 } }, /* 01001 */
906 { 0x0a, { 1, 1, 1 } }, /* 01010 */
907
908 /* Anniedale/Moorefield only configurations */
909 { 0x10, { 4, 2, 0 } }, /* 10000 */
910 { 0x11, { 3, 2, 0 } }, /* 10001 */
911 { 0x12, { 2, 2, 0 } }, /* 10010 */
912 { 0x13, { 1, 2, 0 } }, /* 10011 */
913 { 0x14, { 2, 2, 2 } }, /* 10100 */
914 { 0x18, { 3, 2, 1 } }, /* 11000 */
915 { 0x19, { 2, 2, 1 } }, /* 11001 */
916 { 0x1a, { 1, 2, 1 } }, /* 11010 */
917 };
918
919 unsigned int i, j;
920 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 };
921 u32 csi_control;
922 int nportconfigs;
923 u32 port_config_mask;
924 int port3_lanes_shift;
925
926 if (isp->media_dev.hw_revision <
927 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
928 ATOMISP_HW_REVISION_SHIFT) {
929 /* Merrifield */
930 port_config_mask = MRFLD_PORT_CONFIG_MASK;
931 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
932 } else {
933 /* Moorefield / Cherryview */
934 port_config_mask = CHV_PORT_CONFIG_MASK;
935 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
936 }
937
938 if (isp->media_dev.hw_revision <
939 ATOMISP_HW_REVISION_ISP2401 <<
940 ATOMISP_HW_REVISION_SHIFT) {
941 /* Merrifield / Moorefield legacy input system */
942 nportconfigs = MRFLD_PORT_CONFIG_NUM;
943 } else {
944 /* Moorefield / Cherryview new input system */
945 nportconfigs = ARRAY_SIZE(portconfigs);
946 }
947
948 for (i = 0; i < isp->input_cnt; i++) {
949 struct camera_mipi_info *mipi_info;
950
951 if (isp->inputs[i].type != RAW_CAMERA &&
952 isp->inputs[i].type != SOC_CAMERA)
953 continue;
954
955 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera);
956 if (!mipi_info)
957 continue;
958
959 switch (mipi_info->port) {
960 case ATOMISP_CAMERA_PORT_PRIMARY:
961 sensor_lanes[0] = mipi_info->num_lanes;
962 break;
963 case ATOMISP_CAMERA_PORT_SECONDARY:
964 sensor_lanes[1] = mipi_info->num_lanes;
965 break;
966 case ATOMISP_CAMERA_PORT_TERTIARY:
967 sensor_lanes[2] = mipi_info->num_lanes;
968 break;
969 default:
970 dev_err(isp->dev,
971 "%s: invalid port: %d for the %dth sensor\n",
972 __func__, mipi_info->port, i);
973 return -EINVAL;
974 }
975 }
976
977 for (i = 0; i < nportconfigs; i++) {
978 for (j = 0; j < MRFLD_PORT_NUM; j++)
979 if (sensor_lanes[j] &&
980 sensor_lanes[j] != portconfigs[i].lanes[j])
981 break;
982
983 if (j == MRFLD_PORT_NUM)
984 break; /* Found matching setting */
985 }
986
987 if (i >= nportconfigs) {
988 dev_err(isp->dev,
989 "%s: could not find the CSI port setting for %d-%d-%d\n",
990 __func__,
991 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]);
992 return -EINVAL;
993 }
994
995 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
996 csi_control &= ~port_config_mask;
997 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
998 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
999 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
1000 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
1001 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
1002 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
1003 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
1004
1005 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
1006
1007 dev_dbg(isp->dev,
1008 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
1009 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
1010 portconfigs[i].lanes[2], csi_control);
1011
1012 return 0;
1013 }
1014
atomisp_subdev_probe(struct atomisp_device * isp)1015 static int atomisp_subdev_probe(struct atomisp_device *isp)
1016 {
1017 const struct atomisp_platform_data *pdata;
1018 struct intel_v4l2_subdev_table *subdevs;
1019 int ret, raw_index = -1, count;
1020
1021 pdata = atomisp_get_platform_data();
1022 if (!pdata) {
1023 dev_err(isp->dev, "no platform data available\n");
1024 return 0;
1025 }
1026
1027 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */
1028 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) {
1029 int camera_count = 0;
1030
1031 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
1032 if (subdevs->type == RAW_CAMERA ||
1033 subdevs->type == SOC_CAMERA)
1034 camera_count++;
1035 }
1036 if (camera_count)
1037 break;
1038 msleep(SUBDEV_WAIT_TIMEOUT);
1039 }
1040 /* Wait more time to give more time for subdev init code to finish */
1041 msleep(5 * SUBDEV_WAIT_TIMEOUT);
1042
1043 /* FIXME: should, instead, use I2C probe */
1044
1045 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
1046 struct v4l2_subdev *subdev;
1047 struct i2c_board_info *board_info =
1048 &subdevs->v4l2_subdev.board_info;
1049 struct i2c_adapter *adapter =
1050 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id);
1051 int sensor_num, i;
1052
1053 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type);
1054
1055 if (!adapter) {
1056 dev_err(isp->dev,
1057 "Failed to find i2c adapter for subdev %s\n",
1058 board_info->type);
1059 break;
1060 }
1061
1062 /* In G-Min, the sensor devices will already be probed
1063 * (via ACPI) and registered, do not create new
1064 * ones */
1065 subdev = atomisp_gmin_find_subdev(adapter, board_info);
1066 if (!subdev) {
1067 dev_warn(isp->dev, "Subdev %s not found\n",
1068 board_info->type);
1069 continue;
1070 }
1071 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev);
1072 if (ret) {
1073 dev_warn(isp->dev, "Subdev %s detection fail\n",
1074 board_info->type);
1075 continue;
1076 }
1077
1078 if (!subdev) {
1079 dev_warn(isp->dev, "Subdev %s detection fail\n",
1080 board_info->type);
1081 continue;
1082 }
1083
1084 dev_info(isp->dev, "Subdev %s successfully register\n",
1085 board_info->type);
1086
1087 switch (subdevs->type) {
1088 case RAW_CAMERA:
1089 dev_dbg(isp->dev, "raw_index: %d\n", raw_index);
1090 raw_index = isp->input_cnt;
1091 fallthrough;
1092 case SOC_CAMERA:
1093 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt);
1094 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
1095 dev_warn(isp->dev,
1096 "too many atomisp inputs, ignored\n");
1097 break;
1098 }
1099
1100 isp->inputs[isp->input_cnt].type = subdevs->type;
1101 isp->inputs[isp->input_cnt].port = subdevs->port;
1102 isp->inputs[isp->input_cnt].camera = subdev;
1103 isp->inputs[isp->input_cnt].sensor_index = 0;
1104 /*
1105 * initialize the subdev frame size, then next we can
1106 * judge whether frame_size store effective value via
1107 * pixel_format.
1108 */
1109 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0;
1110 isp->inputs[isp->input_cnt].camera_caps =
1111 atomisp_get_default_camera_caps();
1112 sensor_num = isp->inputs[isp->input_cnt]
1113 .camera_caps->sensor_num;
1114 isp->input_cnt++;
1115 for (i = 1; i < sensor_num; i++) {
1116 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
1117 dev_warn(isp->dev,
1118 "atomisp inputs out of range\n");
1119 break;
1120 }
1121 isp->inputs[isp->input_cnt] =
1122 isp->inputs[isp->input_cnt - 1];
1123 isp->inputs[isp->input_cnt].sensor_index = i;
1124 isp->input_cnt++;
1125 }
1126 break;
1127 case CAMERA_MOTOR:
1128 if (isp->motor) {
1129 dev_warn(isp->dev,
1130 "too many atomisp motors, ignored %s\n",
1131 board_info->type);
1132 continue;
1133 }
1134 isp->motor = subdev;
1135 break;
1136 case LED_FLASH:
1137 case XENON_FLASH:
1138 if (isp->flash) {
1139 dev_warn(isp->dev,
1140 "too many atomisp flash devices, ignored %s\n",
1141 board_info->type);
1142 continue;
1143 }
1144 isp->flash = subdev;
1145 break;
1146 default:
1147 dev_dbg(isp->dev, "unknown subdev probed\n");
1148 break;
1149 }
1150 }
1151
1152 /*
1153 * HACK: Currently VCM belongs to primary sensor only, but correct
1154 * approach must be to acquire from platform code which sensor
1155 * owns it.
1156 */
1157 if (isp->motor && raw_index >= 0)
1158 isp->inputs[raw_index].motor = isp->motor;
1159
1160 /* Proceed even if no modules detected. For COS mode and no modules. */
1161 if (!isp->input_cnt)
1162 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1163 else
1164 dev_info(isp->dev, "detected %d camera sensors\n",
1165 isp->input_cnt);
1166
1167 return atomisp_csi_lane_config(isp);
1168 }
1169
atomisp_unregister_entities(struct atomisp_device * isp)1170 static void atomisp_unregister_entities(struct atomisp_device *isp)
1171 {
1172 unsigned int i;
1173 struct v4l2_subdev *sd, *next;
1174
1175 for (i = 0; i < isp->num_of_streams; i++)
1176 atomisp_subdev_unregister_entities(&isp->asd[i]);
1177 atomisp_tpg_unregister_entities(&isp->tpg);
1178 atomisp_file_input_unregister_entities(&isp->file_dev);
1179 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1180 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1181
1182 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
1183 v4l2_device_unregister_subdev(sd);
1184
1185 v4l2_device_unregister(&isp->v4l2_dev);
1186 media_device_unregister(&isp->media_dev);
1187 media_device_cleanup(&isp->media_dev);
1188 }
1189
atomisp_register_entities(struct atomisp_device * isp)1190 static int atomisp_register_entities(struct atomisp_device *isp)
1191 {
1192 int ret = 0;
1193 unsigned int i;
1194
1195 isp->media_dev.dev = isp->dev;
1196
1197 strscpy(isp->media_dev.model, "Intel Atom ISP",
1198 sizeof(isp->media_dev.model));
1199
1200 media_device_init(&isp->media_dev);
1201 isp->v4l2_dev.mdev = &isp->media_dev;
1202 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1203 if (ret < 0) {
1204 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1205 __func__, ret);
1206 goto v4l2_device_failed;
1207 }
1208
1209 ret = atomisp_subdev_probe(isp);
1210 if (ret < 0)
1211 goto csi_and_subdev_probe_failed;
1212
1213 /* Register internal entities */
1214 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1215 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
1216 &isp->v4l2_dev);
1217 if (ret == 0)
1218 continue;
1219
1220 /* error case */
1221 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
1222 /* deregister all registered CSI ports */
1223 while (i--)
1224 atomisp_mipi_csi2_unregister_entities(
1225 &isp->csi2_port[i]);
1226
1227 goto csi_and_subdev_probe_failed;
1228 }
1229
1230 ret =
1231 atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev);
1232 if (ret < 0) {
1233 dev_err(isp->dev, "atomisp_file_input_register_entities\n");
1234 goto file_input_register_failed;
1235 }
1236
1237 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
1238 if (ret < 0) {
1239 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
1240 goto tpg_register_failed;
1241 }
1242
1243 for (i = 0; i < isp->num_of_streams; i++) {
1244 struct atomisp_sub_device *asd = &isp->asd[i];
1245
1246 ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev);
1247 if (ret < 0) {
1248 dev_err(isp->dev,
1249 "atomisp_subdev_register_entities fail\n");
1250 for (; i > 0; i--)
1251 atomisp_subdev_unregister_entities(
1252 &isp->asd[i - 1]);
1253 goto subdev_register_failed;
1254 }
1255 }
1256
1257 for (i = 0; i < isp->num_of_streams; i++) {
1258 struct atomisp_sub_device *asd = &isp->asd[i];
1259
1260 init_completion(&asd->init_done);
1261
1262 asd->delayed_init_workq =
1263 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
1264 1);
1265 if (!asd->delayed_init_workq) {
1266 dev_err(isp->dev,
1267 "Failed to initialize delayed init workq\n");
1268 ret = -ENOMEM;
1269
1270 for (; i > 0; i--)
1271 destroy_workqueue(isp->asd[i - 1].
1272 delayed_init_workq);
1273 goto wq_alloc_failed;
1274 }
1275 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work);
1276 }
1277
1278 for (i = 0; i < isp->input_cnt; i++) {
1279 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) {
1280 dev_err(isp->dev, "isp->inputs port %d not supported\n",
1281 isp->inputs[i].port);
1282 ret = -EINVAL;
1283 goto link_failed;
1284 }
1285 }
1286
1287 dev_dbg(isp->dev,
1288 "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt);
1289 isp->inputs[isp->input_cnt].type = FILE_INPUT;
1290 isp->inputs[isp->input_cnt].port = -1;
1291 isp->inputs[isp->input_cnt].camera_caps =
1292 atomisp_get_default_camera_caps();
1293 isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd;
1294
1295 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1296 dev_dbg(isp->dev,
1297 "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1298 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1299 isp->inputs[isp->input_cnt].port = -1;
1300 isp->inputs[isp->input_cnt].camera_caps =
1301 atomisp_get_default_camera_caps();
1302 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1303 } else {
1304 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1305 }
1306
1307 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1308 if (ret < 0)
1309 goto link_failed;
1310
1311 return media_device_register(&isp->media_dev);
1312
1313 link_failed:
1314 for (i = 0; i < isp->num_of_streams; i++)
1315 destroy_workqueue(isp->asd[i].
1316 delayed_init_workq);
1317 wq_alloc_failed:
1318 for (i = 0; i < isp->num_of_streams; i++)
1319 atomisp_subdev_unregister_entities(
1320 &isp->asd[i]);
1321 subdev_register_failed:
1322 atomisp_tpg_unregister_entities(&isp->tpg);
1323 tpg_register_failed:
1324 atomisp_file_input_unregister_entities(&isp->file_dev);
1325 file_input_register_failed:
1326 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1327 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1328 csi_and_subdev_probe_failed:
1329 v4l2_device_unregister(&isp->v4l2_dev);
1330 v4l2_device_failed:
1331 media_device_unregister(&isp->media_dev);
1332 media_device_cleanup(&isp->media_dev);
1333 return ret;
1334 }
1335
atomisp_initialize_modules(struct atomisp_device * isp)1336 static int atomisp_initialize_modules(struct atomisp_device *isp)
1337 {
1338 int ret;
1339
1340 ret = atomisp_mipi_csi2_init(isp);
1341 if (ret < 0) {
1342 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1343 goto error_mipi_csi2;
1344 }
1345
1346 ret = atomisp_file_input_init(isp);
1347 if (ret < 0) {
1348 dev_err(isp->dev,
1349 "file input device initialization failed\n");
1350 goto error_file_input;
1351 }
1352
1353 ret = atomisp_tpg_init(isp);
1354 if (ret < 0) {
1355 dev_err(isp->dev, "tpg initialization failed\n");
1356 goto error_tpg;
1357 }
1358
1359 ret = atomisp_subdev_init(isp);
1360 if (ret < 0) {
1361 dev_err(isp->dev, "ISP subdev initialization failed\n");
1362 goto error_isp_subdev;
1363 }
1364
1365 return 0;
1366
1367 error_isp_subdev:
1368 error_tpg:
1369 atomisp_tpg_cleanup(isp);
1370 error_file_input:
1371 atomisp_file_input_cleanup(isp);
1372 error_mipi_csi2:
1373 atomisp_mipi_csi2_cleanup(isp);
1374 return ret;
1375 }
1376
atomisp_uninitialize_modules(struct atomisp_device * isp)1377 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1378 {
1379 atomisp_tpg_cleanup(isp);
1380 atomisp_file_input_cleanup(isp);
1381 atomisp_mipi_csi2_cleanup(isp);
1382 }
1383
1384 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1385 atomisp_load_firmware(struct atomisp_device *isp)
1386 {
1387 const struct firmware *fw;
1388 int rc;
1389 char *fw_path = NULL;
1390
1391 if (skip_fwload)
1392 return NULL;
1393
1394 if (firmware_name[0] != '\0') {
1395 fw_path = firmware_name;
1396 } else {
1397 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1398 == ATOMISP_HW_REVISION_ISP2401)
1399 fw_path = "shisp_2401a0_v21.bin";
1400
1401 if (isp->media_dev.hw_revision ==
1402 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1403 | ATOMISP_HW_STEPPING_A0))
1404 fw_path = "shisp_2401a0_legacy_v21.bin";
1405
1406 if (isp->media_dev.hw_revision ==
1407 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1408 | ATOMISP_HW_STEPPING_B0))
1409 fw_path = "shisp_2400b0_v21.bin";
1410 }
1411
1412 if (!fw_path) {
1413 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1414 isp->media_dev.hw_revision);
1415 return NULL;
1416 }
1417
1418 rc = request_firmware(&fw, fw_path, isp->dev);
1419 if (rc) {
1420 dev_err(isp->dev,
1421 "atomisp: Error %d while requesting firmware %s\n",
1422 rc, fw_path);
1423 return NULL;
1424 }
1425
1426 return fw;
1427 }
1428
1429 /*
1430 * Check for flags the driver was compiled with against the PCI
1431 * device. Always returns true on other than ISP 2400.
1432 */
is_valid_device(struct pci_dev * pdev,const struct pci_device_id * id)1433 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id)
1434 {
1435 const char *name;
1436 const char *product;
1437
1438 product = dmi_get_system_info(DMI_PRODUCT_NAME);
1439
1440 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1441 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1442 name = "Merrifield";
1443 break;
1444 case ATOMISP_PCI_DEVICE_SOC_BYT:
1445 name = "Baytrail";
1446 break;
1447 case ATOMISP_PCI_DEVICE_SOC_ANN:
1448 name = "Anniedale";
1449 break;
1450 case ATOMISP_PCI_DEVICE_SOC_CHT:
1451 name = "Cherrytrail";
1452 break;
1453 default:
1454 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1455 product, id->vendor, id->device);
1456 return false;
1457 }
1458
1459 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1460 dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
1461 name, pdev->revision);
1462 return false;
1463 }
1464
1465 /*
1466 * FIXME:
1467 * remove the if once the driver become generic
1468 */
1469
1470 #if defined(ISP2400)
1471 if (IS_ISP2401) {
1472 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
1473 name);
1474 return false;
1475 }
1476 #else
1477 if (!IS_ISP2401) {
1478 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
1479 name);
1480 return false;
1481 }
1482 #endif
1483
1484 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1485 name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1486
1487 return true;
1488 }
1489
init_atomisp_wdts(struct atomisp_device * isp)1490 static int init_atomisp_wdts(struct atomisp_device *isp)
1491 {
1492 int i, err;
1493
1494 atomic_set(&isp->wdt_work_queued, 0);
1495 isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
1496 if (!isp->wdt_work_queue) {
1497 dev_err(isp->dev, "Failed to initialize wdt work queue\n");
1498 err = -ENOMEM;
1499 goto alloc_fail;
1500 }
1501 INIT_WORK(&isp->wdt_work, atomisp_wdt_work);
1502
1503 for (i = 0; i < isp->num_of_streams; i++) {
1504 struct atomisp_sub_device *asd = &isp->asd[i];
1505
1506 if (!IS_ISP2401)
1507 timer_setup(&asd->wdt, atomisp_wdt, 0);
1508 else {
1509 timer_setup(&asd->video_out_capture.wdt,
1510 atomisp_wdt, 0);
1511 timer_setup(&asd->video_out_preview.wdt,
1512 atomisp_wdt, 0);
1513 timer_setup(&asd->video_out_vf.wdt, atomisp_wdt, 0);
1514 timer_setup(&asd->video_out_video_capture.wdt,
1515 atomisp_wdt, 0);
1516 }
1517 }
1518 return 0;
1519 alloc_fail:
1520 return err;
1521 }
1522
1523 #define ATOM_ISP_PCI_BAR 0
1524
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1525 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1526 {
1527 const struct atomisp_platform_data *pdata;
1528 struct atomisp_device *isp;
1529 unsigned int start;
1530 int err, val;
1531 u32 irq;
1532
1533 if (!is_valid_device(pdev, id))
1534 return -ENODEV;
1535
1536 /* Pointer to struct device. */
1537 atomisp_dev = &pdev->dev;
1538
1539 pdata = atomisp_get_platform_data();
1540 if (!pdata)
1541 dev_warn(&pdev->dev, "no platform data available\n");
1542
1543 err = pcim_enable_device(pdev);
1544 if (err) {
1545 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1546 return err;
1547 }
1548
1549 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1550 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1551
1552 err = pcim_iomap_regions(pdev, 1 << ATOM_ISP_PCI_BAR, pci_name(pdev));
1553 if (err) {
1554 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1555 goto ioremap_fail;
1556 }
1557
1558 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1559 if (!isp) {
1560 err = -ENOMEM;
1561 goto atomisp_dev_alloc_fail;
1562 }
1563
1564 isp->dev = &pdev->dev;
1565 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1566 isp->sw_contex.power_state = ATOM_ISP_POWER_UP;
1567 isp->saved_regs.ispmmadr = start;
1568
1569 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
1570
1571 rt_mutex_init(&isp->mutex);
1572 mutex_init(&isp->streamoff_mutex);
1573 spin_lock_init(&isp->lock);
1574
1575 /* This is not a true PCI device on SoC, so the delay is not needed. */
1576 pdev->d3hot_delay = 0;
1577
1578 pci_set_drvdata(pdev, isp);
1579
1580 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1581 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1582 isp->media_dev.hw_revision =
1583 (ATOMISP_HW_REVISION_ISP2400
1584 << ATOMISP_HW_REVISION_SHIFT) |
1585 ATOMISP_HW_STEPPING_B0;
1586
1587 switch (id->device) {
1588 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1589 isp->dfs = &dfs_config_merr_1179;
1590 break;
1591 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1592 isp->dfs = &dfs_config_merr_117a;
1593
1594 break;
1595 default:
1596 isp->dfs = &dfs_config_merr;
1597 break;
1598 }
1599 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1600 break;
1601 case ATOMISP_PCI_DEVICE_SOC_BYT:
1602 isp->media_dev.hw_revision =
1603 (ATOMISP_HW_REVISION_ISP2400
1604 << ATOMISP_HW_REVISION_SHIFT) |
1605 ATOMISP_HW_STEPPING_B0;
1606
1607 /*
1608 * Note: some Intel-based tablets with Android use a different
1609 * DFS table. Based on the comments at the Yocto Aero meta
1610 * version of this driver (at the ssid.h header), they're
1611 * identified via a "spid" var:
1612 *
1613 * androidboot.spid=vend:cust:manu:plat:prod:hard
1614 *
1615 * As we don't have this upstream, nor we know enough details
1616 * to use a DMI or PCI match table, the old code was just
1617 * removed, but let's keep a note here as a reminder that,
1618 * for certain devices, we may need to limit the max DFS
1619 * frequency to be below certain values, adjusting the
1620 * resolution accordingly.
1621 */
1622 isp->dfs = &dfs_config_byt;
1623
1624 /*
1625 * HPLL frequency is known to be device-specific, but we don't
1626 * have specs yet for exactly how it varies. Default to
1627 * BYT-CR but let provisioning set it via EFI variable
1628 */
1629 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1630
1631 /*
1632 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1633 * in power off. Set d3cold_delay to 0 since default 100ms is not
1634 * necessary.
1635 */
1636 pdev->d3cold_delay = 0;
1637 break;
1638 case ATOMISP_PCI_DEVICE_SOC_ANN:
1639 isp->media_dev.hw_revision = (
1640 #ifdef ISP2401_NEW_INPUT_SYSTEM
1641 ATOMISP_HW_REVISION_ISP2401
1642 #else
1643 ATOMISP_HW_REVISION_ISP2401_LEGACY
1644 #endif
1645 << ATOMISP_HW_REVISION_SHIFT);
1646 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1647 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1648 isp->dfs = &dfs_config_merr;
1649 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1650 break;
1651 case ATOMISP_PCI_DEVICE_SOC_CHT:
1652 isp->media_dev.hw_revision = (
1653 #ifdef ISP2401_NEW_INPUT_SYSTEM
1654 ATOMISP_HW_REVISION_ISP2401
1655 #else
1656 ATOMISP_HW_REVISION_ISP2401_LEGACY
1657 #endif
1658 << ATOMISP_HW_REVISION_SHIFT);
1659 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1660 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1661
1662 isp->dfs = &dfs_config_cht;
1663 pdev->d3cold_delay = 0;
1664
1665 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1666 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1667 case 0x00:
1668 isp->hpll_freq = HPLL_FREQ_800MHZ;
1669 break;
1670 case 0x01:
1671 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1672 break;
1673 case 0x02:
1674 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1675 break;
1676 default:
1677 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1678 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1679 }
1680 break;
1681 default:
1682 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1683 err = -ENODEV;
1684 goto atomisp_dev_alloc_fail;
1685 }
1686
1687 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1688
1689 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1690
1691 /* Load isp firmware from user space */
1692 if (!defer_fw_load) {
1693 isp->firmware = atomisp_load_firmware(isp);
1694 if (!isp->firmware) {
1695 err = -ENOENT;
1696 dev_dbg(&pdev->dev, "Firmware load failed\n");
1697 goto load_fw_fail;
1698 }
1699
1700 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1701 if (err) {
1702 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1703 goto fw_validation_fail;
1704 }
1705 } else {
1706 dev_info(&pdev->dev, "Firmware load will be deferred\n");
1707 }
1708
1709 pci_set_master(pdev);
1710
1711 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1712 if (err < 0) {
1713 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1714 goto enable_msi_fail;
1715 }
1716
1717 atomisp_msi_irq_init(isp);
1718
1719 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1720
1721 /*
1722 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1723 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1724 * backend write 0 will enable Arasan CSI backend, which has
1725 * bugs(like sighting:4567697 and 4567699) and will be removed
1726 * in B0
1727 */
1728 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1729
1730 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1731 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1732 u32 csi_afe_trim;
1733
1734 /*
1735 * Workaround for imbalance data eye issue which is observed
1736 * on TNG B0.
1737 */
1738 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1739 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1740 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1741 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1742 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1743 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1744 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1745 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1746 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1747 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1748 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1749 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1750 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1751 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1752 }
1753
1754 err = atomisp_initialize_modules(isp);
1755 if (err < 0) {
1756 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1757 goto initialize_modules_fail;
1758 }
1759
1760 err = atomisp_register_entities(isp);
1761 if (err < 0) {
1762 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1763 goto register_entities_fail;
1764 }
1765 err = atomisp_create_pads_links(isp);
1766 if (err < 0)
1767 goto register_entities_fail;
1768 /* init atomisp wdts */
1769 err = init_atomisp_wdts(isp);
1770 if (err != 0)
1771 goto wdt_work_queue_fail;
1772
1773 /* save the iunit context only once after all the values are init'ed. */
1774 atomisp_save_iunit_reg(isp);
1775
1776 pm_runtime_put_noidle(&pdev->dev);
1777 pm_runtime_allow(&pdev->dev);
1778
1779 hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr);
1780 err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED);
1781 if (err) {
1782 dev_err(&pdev->dev, "Failed to register reserved memory pool.\n");
1783 goto hmm_pool_fail;
1784 }
1785
1786 /* Init ISP memory management */
1787 hmm_init();
1788
1789 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1790 atomisp_isr, atomisp_isr_thread,
1791 IRQF_SHARED, "isp_irq", isp);
1792 if (err) {
1793 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1794 goto request_irq_fail;
1795 }
1796
1797 /* Load firmware into ISP memory */
1798 if (!defer_fw_load) {
1799 err = atomisp_css_load_firmware(isp);
1800 if (err) {
1801 dev_err(&pdev->dev, "Failed to init css.\n");
1802 goto css_init_fail;
1803 }
1804 } else {
1805 dev_dbg(&pdev->dev, "Skip css init.\n");
1806 }
1807 /* Clear FW image from memory */
1808 release_firmware(isp->firmware);
1809 isp->firmware = NULL;
1810 isp->css_env.isp_css_fw.data = NULL;
1811
1812 atomisp_drvfs_init(isp);
1813
1814 return 0;
1815
1816 css_init_fail:
1817 devm_free_irq(&pdev->dev, pdev->irq, isp);
1818 request_irq_fail:
1819 hmm_cleanup();
1820 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1821 hmm_pool_fail:
1822 pm_runtime_get_noresume(&pdev->dev);
1823 destroy_workqueue(isp->wdt_work_queue);
1824 wdt_work_queue_fail:
1825 atomisp_acc_cleanup(isp);
1826 atomisp_unregister_entities(isp);
1827 register_entities_fail:
1828 atomisp_uninitialize_modules(isp);
1829 initialize_modules_fail:
1830 cpu_latency_qos_remove_request(&isp->pm_qos);
1831 atomisp_msi_irq_uninit(isp);
1832 pci_free_irq_vectors(pdev);
1833 enable_msi_fail:
1834 fw_validation_fail:
1835 release_firmware(isp->firmware);
1836 load_fw_fail:
1837 /*
1838 * Switch off ISP, as keeping it powered on would prevent
1839 * reaching S0ix states.
1840 *
1841 * The following lines have been copied from atomisp suspend path
1842 */
1843
1844 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1845 irq = irq & 1 << INTR_IIR;
1846 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1847
1848 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1849 irq &= ~(1 << INTR_IER);
1850 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1851
1852 atomisp_msi_irq_uninit(isp);
1853
1854 atomisp_ospm_dphy_down(isp);
1855
1856 /* Address later when we worry about the ...field chips */
1857 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp))
1858 dev_err(&pdev->dev, "Failed to switch off ISP\n");
1859
1860 atomisp_dev_alloc_fail:
1861 pcim_iounmap_regions(pdev, 1 << ATOM_ISP_PCI_BAR);
1862
1863 ioremap_fail:
1864 return err;
1865 }
1866
atomisp_pci_remove(struct pci_dev * pdev)1867 static void atomisp_pci_remove(struct pci_dev *pdev)
1868 {
1869 struct atomisp_device *isp = pci_get_drvdata(pdev);
1870
1871 dev_info(&pdev->dev, "Removing atomisp driver\n");
1872
1873 atomisp_drvfs_exit();
1874
1875 atomisp_acc_cleanup(isp);
1876
1877 ia_css_unload_firmware();
1878 hmm_cleanup();
1879
1880 pm_runtime_forbid(&pdev->dev);
1881 pm_runtime_get_noresume(&pdev->dev);
1882 cpu_latency_qos_remove_request(&isp->pm_qos);
1883
1884 atomisp_msi_irq_uninit(isp);
1885 atomisp_unregister_entities(isp);
1886
1887 destroy_workqueue(isp->wdt_work_queue);
1888 atomisp_file_input_cleanup(isp);
1889
1890 release_firmware(isp->firmware);
1891
1892 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1893 }
1894
1895 static const struct pci_device_id atomisp_pci_tbl[] = {
1896 /* Merrifield */
1897 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1898 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1899 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1900 /* Baytrail */
1901 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1902 /* Anniedale (Merrifield+ / Moorefield) */
1903 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1904 /* Cherrytrail */
1905 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1906 {0,}
1907 };
1908
1909 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1910
1911 static const struct dev_pm_ops atomisp_pm_ops = {
1912 .runtime_suspend = atomisp_runtime_suspend,
1913 .runtime_resume = atomisp_runtime_resume,
1914 .suspend = atomisp_suspend,
1915 .resume = atomisp_resume,
1916 };
1917
1918 static struct pci_driver atomisp_pci_driver = {
1919 .driver = {
1920 .pm = &atomisp_pm_ops,
1921 },
1922 .name = "atomisp-isp2",
1923 .id_table = atomisp_pci_tbl,
1924 .probe = atomisp_pci_probe,
1925 .remove = atomisp_pci_remove,
1926 };
1927
1928 module_pci_driver(atomisp_pci_driver);
1929
1930 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1931 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1932 MODULE_LICENSE("GPL");
1933 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1934