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Searched refs:DCFE_MEM_PWR_CTRL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c179 if (REG(DCFE_MEM_PWR_CTRL)) in dce_ipp_program_input_lut()
180 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
211 if (REG(DCFE_MEM_PWR_CTRL)) in dce_ipp_program_input_lut()
212 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
Ddce_transform.c224 if (REG(DCFE_MEM_PWR_CTRL)) { in program_multi_taps_filter()
225 power_ctl = REG_READ(DCFE_MEM_PWR_CTRL); in program_multi_taps_filter()
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
258 if (REG(DCFE_MEM_PWR_CTRL)) in program_multi_taps_filter()
259 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); in program_multi_taps_filter()
1432 if (REG(DCFE_MEM_PWR_CTRL)) in program_pwl()
1433 REG_UPDATE(DCFE_MEM_PWR_CTRL, in program_pwl()
1486 if (REG(DCFE_MEM_PWR_CTRL)) in program_pwl()
1487 REG_UPDATE(DCFE_MEM_PWR_CTRL, in program_pwl()
1590 if (REG(DCFE_MEM_PWR_CTRL)) in dce110_opp_power_on_regamma_lut()
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Ddce_ipp.h58 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
62 SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
108 IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
253 uint32_t DCFE_MEM_PWR_CTRL; member
Ddce_transform.h103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
108 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
262 XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
264 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
265 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
583 uint32_t DCFE_MEM_PWR_CTRL; member