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Searched refs:DCLK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/pm/inc/
Dpower_state.h144 uint32_t DCLK; member
/drivers/gpu/drm/i915/gt/
Dintel_llc.c62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dprocesspptables.c763 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); in init_non_clock_fields()
766 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
Dsmu10_hwmgr.c850 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
Dsmu7_hwmgr.c3262 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3355 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3503 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
Dsmu8_hwmgr.c1416 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
Dvega10_hwmgr.c3141 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3219 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c155 CLK_MAP(DCLK, PPCLK_DCLK),
Darcturus_ppt.c154 CLK_MAP(DCLK, PPCLK_DCLK),
Dsienna_cichlid_ppt.c139 CLK_MAP(DCLK, PPCLK_DCLK_0),
/drivers/gpu/drm/i915/
Di915_reg.h3760 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro