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Searched refs:DCN10TG_FROM_TG (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c50 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_enable_crtc()
82 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_timing_db_mode()
97 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_gsl()
117 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_use_gsl_as_master_update_lock()
127 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_gsl_window()
145 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_vupdate_keepout()
158 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_gsl_source_select()
180 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_dsc_encoder_frame_start()
197 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_dsc_config()
218 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_odm_bypass()
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Ddcn20_resource.c1520 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); in dcn20_resource_destruct()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c67 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_program_global_sync()
92 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_disable_stereo()
107 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_setup_vertical_interrupt0()
118 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_setup_vertical_interrupt1()
128 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_setup_vertical_interrupt2()
159 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_program_timing()
326 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_set_vtg_params()
361 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_set_blank_data_double_buffer()
379 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_set_timing_double_buffer()
392 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc1_unblank_crtc()
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Ddcn10_hw_sequencer_debug.c431 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_get_otg_states()
497 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_clear_otpc_underflow()
Ddcn10_optc.h31 #define DCN10TG_FROM_TG(tg)\ macro
Ddcn10_resource.c1006 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); in dcn10_resource_destruct()
Ddcn10_hw_sequencer.c346 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_log_hw_state()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c43 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_triplebuffer_lock()
62 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock_doublebuffer_enable()
90 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock_doublebuffer_disable()
105 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock()
121 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_set_out_mux()
129 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_program_blank_color()
145 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_set_drr_trigger_window()
155 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_set_vtotal_change_limit()
173 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_set_dsc_config()
185 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_set_odm_bypass()
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Ddcn30_resource.c1270 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); in dcn30_resource_destruct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c971 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); in dcn21_resource_destruct()