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Searched refs:DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_powertune.c188 … DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, …
330 … DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, …
472 … DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, …
616 … DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, …
800 … DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, …
Dvega10_powertune.c225 …L0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0…
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h18362 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 macro
Dgfx_8_0_sh_mask.h20600 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 macro
Dgfx_8_1_sh_mask.h21206 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h29222 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT macro
Dgc_9_1_sh_mask.h30433 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT macro
Dgc_9_2_1_sh_mask.h30706 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT macro
Dgc_10_3_0_sh_mask.h47243 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT macro
Dgc_10_1_0_sh_mask.h43478 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT macro