Searched refs:DISPC_VID_CSC_COEF (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/tidss/ |
| D | tidss_dispc.c | 1388 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), in dispc_k2g_vid_write_csc()
1389 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), in dispc_k2g_vid_write_csc()
1390 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), in dispc_k2g_vid_write_csc()
1391 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */ in dispc_k2g_vid_write_csc()
1411 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), in dispc_k3_vid_write_csc()
1412 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), in dispc_k3_vid_write_csc()
1413 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), in dispc_k3_vid_write_csc()
1414 DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7, in dispc_k3_vid_write_csc()
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| D | tidss_dispc_regs.h | 112 #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) macro
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