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Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c221 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()
223 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()
333 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()
335 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
361 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
377 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
409 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()
411 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
817 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
Doaktrail_hdmi.c359 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()
393 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
394 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
461 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
462 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
Doaktrail_crtc.c269 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()
271 temp | DISPLAY_PLANE_ENABLE, in oaktrail_crtc_dpms()
295 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()
297 temp & ~DISPLAY_PLANE_ENABLE, i); in oaktrail_crtc_dpms()
Dgma_display.c233 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in gma_crtc_dpms()
235 temp | DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
282 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in gma_crtc_dpms()
284 temp & ~DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
Dmdfld_device.c348 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
Dpsb_intel_display.c201 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h624 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
Dcdv_intel_display.c722 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/gvt/
Ddisplay.c187 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
498 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
Dfb_decoder.c214 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); in intel_vgpu_decode_primary_plane()
/drivers/gpu/drm/i915/display/
Dintel_display.c4241 dspcntr = DISPLAY_PLANE_ENABLE; in i9xx_plane_ctl()
4545 ret = val & DISPLAY_PLANE_ENABLE; in i9xx_plane_get_hw_state()
18143 DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
18146 DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
18149 DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
/drivers/gpu/drm/i915/
Di915_reg.h6483 #define DISPLAY_PLANE_ENABLE (1 << 31) macro