1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/android_kabi.h>
21
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
25
26 /* max buffer size for trace and debug messages */
27 #define XHCI_MSG_MAX 500
28
29 /* xHCI PCI Configuration Registers */
30 #define XHCI_SBRN_OFFSET (0x60)
31
32 /* Max number of USB devices for any host controller - limit in section 6.1 */
33 #define MAX_HC_SLOTS 256
34 /* Section 5.3.3 - MaxPorts */
35 #define MAX_HC_PORTS 127
36
37 /*
38 * xHCI register interface.
39 * This corresponds to the eXtensible Host Controller Interface (xHCI)
40 * Revision 0.95 specification
41 */
42
43 /**
44 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
45 * @hc_capbase: length of the capabilities register and HC version number
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
52 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
53 */
54 struct xhci_cap_regs {
55 __le32 hc_capbase;
56 __le32 hcs_params1;
57 __le32 hcs_params2;
58 __le32 hcs_params3;
59 __le32 hcc_params;
60 __le32 db_off;
61 __le32 run_regs_off;
62 __le32 hcc_params2; /* xhci 1.1 */
63 /* Reserved up to (CAPLENGTH - 0x1C) */
64 };
65
66 /* hc_capbase bitmasks */
67 /* bits 7:0 - how long is the Capabilities register */
68 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
69 /* bits 31:16 */
70 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
71
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
73 /* bits 0:7, Max Device Slots */
74 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
75 #define HCS_SLOTS_MASK 0xff
76 /* bits 8:18, Max Interrupters */
77 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
78 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
79 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
80
81 /* HCSPARAMS2 - hcs_params2 - bitmasks */
82 /* bits 0:3, frames or uframes that SW needs to queue transactions
83 * ahead of the HW to meet periodic deadlines */
84 #define HCS_IST(p) (((p) >> 0) & 0xf)
85 /* bits 4:7, max number of Event Ring segments */
86 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
87 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
88 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
89 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
90 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
91
92 /* HCSPARAMS3 - hcs_params3 - bitmasks */
93 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
94 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
95 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
96 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
97
98 /* HCCPARAMS - hcc_params - bitmasks */
99 /* true: HC can use 64-bit address pointers */
100 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
101 /* true: HC can do bandwidth negotiation */
102 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
103 /* true: HC uses 64-byte Device Context structures
104 * FIXME 64-byte context structures aren't supported yet.
105 */
106 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
107 /* true: HC has port power switches */
108 #define HCC_PPC(p) ((p) & (1 << 3))
109 /* true: HC has port indicators */
110 #define HCS_INDICATOR(p) ((p) & (1 << 4))
111 /* true: HC has Light HC Reset Capability */
112 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
113 /* true: HC supports latency tolerance messaging */
114 #define HCC_LTC(p) ((p) & (1 << 6))
115 /* true: no secondary Stream ID Support */
116 #define HCC_NSS(p) ((p) & (1 << 7))
117 /* true: HC supports Stopped - Short Packet */
118 #define HCC_SPC(p) ((p) & (1 << 9))
119 /* true: HC has Contiguous Frame ID Capability */
120 #define HCC_CFC(p) ((p) & (1 << 11))
121 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
122 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
123 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
124 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
125
126 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
127
128 /* db_off bitmask - bits 0:1 reserved */
129 #define DBOFF_MASK (~0x3)
130
131 /* run_regs_off bitmask - bits 0:4 reserved */
132 #define RTSOFF_MASK (~0x1f)
133
134 /* HCCPARAMS2 - hcc_params2 - bitmasks */
135 /* true: HC supports U3 entry Capability */
136 #define HCC2_U3C(p) ((p) & (1 << 0))
137 /* true: HC supports Configure endpoint command Max exit latency too large */
138 #define HCC2_CMC(p) ((p) & (1 << 1))
139 /* true: HC supports Force Save context Capability */
140 #define HCC2_FSC(p) ((p) & (1 << 2))
141 /* true: HC supports Compliance Transition Capability */
142 #define HCC2_CTC(p) ((p) & (1 << 3))
143 /* true: HC support Large ESIT payload Capability > 48k */
144 #define HCC2_LEC(p) ((p) & (1 << 4))
145 /* true: HC support Configuration Information Capability */
146 #define HCC2_CIC(p) ((p) & (1 << 5))
147 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
148 #define HCC2_ETC(p) ((p) & (1 << 6))
149
150 /* Number of registers per port */
151 #define NUM_PORT_REGS 4
152
153 #define PORTSC 0
154 #define PORTPMSC 1
155 #define PORTLI 2
156 #define PORTHLPMC 3
157
158 /**
159 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
160 * @command: USBCMD - xHC command register
161 * @status: USBSTS - xHC status register
162 * @page_size: This indicates the page size that the host controller
163 * supports. If bit n is set, the HC supports a page size
164 * of 2^(n+12), up to a 128MB page size.
165 * 4K is the minimum page size.
166 * @cmd_ring: CRP - 64-bit Command Ring Pointer
167 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
168 * @config_reg: CONFIG - Configure Register
169 * @port_status_base: PORTSCn - base address for Port Status and Control
170 * Each port has a Port Status and Control register,
171 * followed by a Port Power Management Status and Control
172 * register, a Port Link Info register, and a reserved
173 * register.
174 * @port_power_base: PORTPMSCn - base address for
175 * Port Power Management Status and Control
176 * @port_link_base: PORTLIn - base address for Port Link Info (current
177 * Link PM state and control) for USB 2.1 and USB 3.0
178 * devices.
179 */
180 struct xhci_op_regs {
181 __le32 command;
182 __le32 status;
183 __le32 page_size;
184 __le32 reserved1;
185 __le32 reserved2;
186 __le32 dev_notification;
187 __le64 cmd_ring;
188 /* rsvd: offset 0x20-2F */
189 __le32 reserved3[4];
190 __le64 dcbaa_ptr;
191 __le32 config_reg;
192 /* rsvd: offset 0x3C-3FF */
193 __le32 reserved4[241];
194 /* port 1 registers, which serve as a base address for other ports */
195 __le32 port_status_base;
196 __le32 port_power_base;
197 __le32 port_link_base;
198 __le32 reserved5;
199 /* registers for ports 2-255 */
200 __le32 reserved6[NUM_PORT_REGS*254];
201 };
202
203 /* USBCMD - USB command - command bitmasks */
204 /* start/stop HC execution - do not write unless HC is halted*/
205 #define CMD_RUN XHCI_CMD_RUN
206 /* Reset HC - resets internal HC state machine and all registers (except
207 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
208 * The xHCI driver must reinitialize the xHC after setting this bit.
209 */
210 #define CMD_RESET (1 << 1)
211 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
212 #define CMD_EIE XHCI_CMD_EIE
213 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
214 #define CMD_HSEIE XHCI_CMD_HSEIE
215 /* bits 4:6 are reserved (and should be preserved on writes). */
216 /* light reset (port status stays unchanged) - reset completed when this is 0 */
217 #define CMD_LRESET (1 << 7)
218 /* host controller save/restore state. */
219 #define CMD_CSS (1 << 8)
220 #define CMD_CRS (1 << 9)
221 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
222 #define CMD_EWE XHCI_CMD_EWE
223 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
224 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
225 * '0' means the xHC can power it off if all ports are in the disconnect,
226 * disabled, or powered-off state.
227 */
228 #define CMD_PM_INDEX (1 << 11)
229 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
230 #define CMD_ETE (1 << 14)
231 /* bits 15:31 are reserved (and should be preserved on writes). */
232
233 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
234 #define XHCI_RESET_SHORT_USEC (250 * 1000)
235
236 /* IMAN - Interrupt Management Register */
237 #define IMAN_IE (1 << 1)
238 #define IMAN_IP (1 << 0)
239
240 /* USBSTS - USB status - status bitmasks */
241 /* HC not running - set to 1 when run/stop bit is cleared. */
242 #define STS_HALT XHCI_STS_HALT
243 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
244 #define STS_FATAL (1 << 2)
245 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
246 #define STS_EINT (1 << 3)
247 /* port change detect */
248 #define STS_PORT (1 << 4)
249 /* bits 5:7 reserved and zeroed */
250 /* save state status - '1' means xHC is saving state */
251 #define STS_SAVE (1 << 8)
252 /* restore state status - '1' means xHC is restoring state */
253 #define STS_RESTORE (1 << 9)
254 /* true: save or restore error */
255 #define STS_SRE (1 << 10)
256 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
257 #define STS_CNR XHCI_STS_CNR
258 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
259 #define STS_HCE (1 << 12)
260 /* bits 13:31 reserved and should be preserved */
261
262 /*
263 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
264 * Generate a device notification event when the HC sees a transaction with a
265 * notification type that matches a bit set in this bit field.
266 */
267 #define DEV_NOTE_MASK (0xffff)
268 #define ENABLE_DEV_NOTE(x) (1 << (x))
269 /* Most of the device notification types should only be used for debug.
270 * SW does need to pay attention to function wake notifications.
271 */
272 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
273
274 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
275 /* bit 0 is the command ring cycle state */
276 /* stop ring operation after completion of the currently executing command */
277 #define CMD_RING_PAUSE (1 << 1)
278 /* stop ring immediately - abort the currently executing command */
279 #define CMD_RING_ABORT (1 << 2)
280 /* true: command ring is running */
281 #define CMD_RING_RUNNING (1 << 3)
282 /* bits 4:5 reserved and should be preserved */
283 /* Command Ring pointer - bit mask for the lower 32 bits. */
284 #define CMD_RING_RSVD_BITS (0x3f)
285
286 /* CONFIG - Configure Register - config_reg bitmasks */
287 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
288 #define MAX_DEVS(p) ((p) & 0xff)
289 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
290 #define CONFIG_U3E (1 << 8)
291 /* bit 9: Configuration Information Enable, xhci 1.1 */
292 #define CONFIG_CIE (1 << 9)
293 /* bits 10:31 - reserved and should be preserved */
294
295 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
296 /* true: device connected */
297 #define PORT_CONNECT (1 << 0)
298 /* true: port enabled */
299 #define PORT_PE (1 << 1)
300 /* bit 2 reserved and zeroed */
301 /* true: port has an over-current condition */
302 #define PORT_OC (1 << 3)
303 /* true: port reset signaling asserted */
304 #define PORT_RESET (1 << 4)
305 /* Port Link State - bits 5:8
306 * A read gives the current link PM state of the port,
307 * a write with Link State Write Strobe set sets the link state.
308 */
309 #define PORT_PLS_MASK (0xf << 5)
310 #define XDEV_U0 (0x0 << 5)
311 #define XDEV_U1 (0x1 << 5)
312 #define XDEV_U2 (0x2 << 5)
313 #define XDEV_U3 (0x3 << 5)
314 #define XDEV_DISABLED (0x4 << 5)
315 #define XDEV_RXDETECT (0x5 << 5)
316 #define XDEV_INACTIVE (0x6 << 5)
317 #define XDEV_POLLING (0x7 << 5)
318 #define XDEV_RECOVERY (0x8 << 5)
319 #define XDEV_HOT_RESET (0x9 << 5)
320 #define XDEV_COMP_MODE (0xa << 5)
321 #define XDEV_TEST_MODE (0xb << 5)
322 #define XDEV_RESUME (0xf << 5)
323
324 /* true: port has power (see HCC_PPC) */
325 #define PORT_POWER (1 << 9)
326 /* bits 10:13 indicate device speed:
327 * 0 - undefined speed - port hasn't be initialized by a reset yet
328 * 1 - full speed
329 * 2 - low speed
330 * 3 - high speed
331 * 4 - super speed
332 * 5-15 reserved
333 */
334 #define DEV_SPEED_MASK (0xf << 10)
335 #define XDEV_FS (0x1 << 10)
336 #define XDEV_LS (0x2 << 10)
337 #define XDEV_HS (0x3 << 10)
338 #define XDEV_SS (0x4 << 10)
339 #define XDEV_SSP (0x5 << 10)
340 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
341 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
342 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
343 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
344 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
345 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
346 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
347 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
348
349 /* Bits 20:23 in the Slot Context are the speed for the device */
350 #define SLOT_SPEED_FS (XDEV_FS << 10)
351 #define SLOT_SPEED_LS (XDEV_LS << 10)
352 #define SLOT_SPEED_HS (XDEV_HS << 10)
353 #define SLOT_SPEED_SS (XDEV_SS << 10)
354 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
355 /* Port Indicator Control */
356 #define PORT_LED_OFF (0 << 14)
357 #define PORT_LED_AMBER (1 << 14)
358 #define PORT_LED_GREEN (2 << 14)
359 #define PORT_LED_MASK (3 << 14)
360 /* Port Link State Write Strobe - set this when changing link state */
361 #define PORT_LINK_STROBE (1 << 16)
362 /* true: connect status change */
363 #define PORT_CSC (1 << 17)
364 /* true: port enable change */
365 #define PORT_PEC (1 << 18)
366 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
367 * into an enabled state, and the device into the default state. A "warm" reset
368 * also resets the link, forcing the device through the link training sequence.
369 * SW can also look at the Port Reset register to see when warm reset is done.
370 */
371 #define PORT_WRC (1 << 19)
372 /* true: over-current change */
373 #define PORT_OCC (1 << 20)
374 /* true: reset change - 1 to 0 transition of PORT_RESET */
375 #define PORT_RC (1 << 21)
376 /* port link status change - set on some port link state transitions:
377 * Transition Reason
378 * ------------------------------------------------------------------------------
379 * - U3 to Resume Wakeup signaling from a device
380 * - Resume to Recovery to U0 USB 3.0 device resume
381 * - Resume to U0 USB 2.0 device resume
382 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
383 * - U3 to U0 Software resume of USB 2.0 device complete
384 * - U2 to U0 L1 resume of USB 2.1 device complete
385 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
386 * - U0 to disabled L1 entry error with USB 2.1 device
387 * - Any state to inactive Error on USB 3.0 port
388 */
389 #define PORT_PLC (1 << 22)
390 /* port configure error change - port failed to configure its link partner */
391 #define PORT_CEC (1 << 23)
392 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
393 PORT_RC | PORT_PLC | PORT_CEC)
394
395
396 /* Cold Attach Status - xHC can set this bit to report device attached during
397 * Sx state. Warm port reset should be perfomed to clear this bit and move port
398 * to connected state.
399 */
400 #define PORT_CAS (1 << 24)
401 /* wake on connect (enable) */
402 #define PORT_WKCONN_E (1 << 25)
403 /* wake on disconnect (enable) */
404 #define PORT_WKDISC_E (1 << 26)
405 /* wake on over-current (enable) */
406 #define PORT_WKOC_E (1 << 27)
407 /* bits 28:29 reserved */
408 /* true: device is non-removable - for USB 3.0 roothub emulation */
409 #define PORT_DEV_REMOVE (1 << 30)
410 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
411 #define PORT_WR (1 << 31)
412
413 /* We mark duplicate entries with -1 */
414 #define DUPLICATE_ENTRY ((u8)(-1))
415
416 /* Port Power Management Status and Control - port_power_base bitmasks */
417 /* Inactivity timer value for transitions into U1, in microseconds.
418 * Timeout can be up to 127us. 0xFF means an infinite timeout.
419 */
420 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
421 #define PORT_U1_TIMEOUT_MASK 0xff
422 /* Inactivity timer value for transitions into U2 */
423 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
424 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
425 /* Bits 24:31 for port testing */
426
427 /* USB2 Protocol PORTSPMSC */
428 #define PORT_L1S_MASK 7
429 #define PORT_L1S_SUCCESS 1
430 #define PORT_RWE (1 << 3)
431 #define PORT_HIRD(p) (((p) & 0xf) << 4)
432 #define PORT_HIRD_MASK (0xf << 4)
433 #define PORT_L1DS_MASK (0xff << 8)
434 #define PORT_L1DS(p) (((p) & 0xff) << 8)
435 #define PORT_HLE (1 << 16)
436 #define PORT_TEST_MODE_SHIFT 28
437
438 /* USB3 Protocol PORTLI Port Link Information */
439 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
440 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
441
442 /* USB2 Protocol PORTHLPMC */
443 #define PORT_HIRDM(p)((p) & 3)
444 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
445 #define PORT_BESLD(p)(((p) & 0xf) << 10)
446
447 /* use 512 microseconds as USB2 LPM L1 default timeout. */
448 #define XHCI_L1_TIMEOUT 512
449
450 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
451 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
452 * by other operating systems.
453 *
454 * XHCI 1.0 errata 8/14/12 Table 13 notes:
455 * "Software should choose xHC BESL/BESLD field values that do not violate a
456 * device's resume latency requirements,
457 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
458 * or not program values < '4' if BLC = '0' and a BESL device is attached.
459 */
460 #define XHCI_DEFAULT_BESL 4
461
462 /*
463 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
464 * to complete link training. usually link trainig completes much faster
465 * so check status 10 times with 36ms sleep in places we need to wait for
466 * polling to complete.
467 */
468 #define XHCI_PORT_POLLING_LFPS_TIME 36
469
470 /**
471 * struct xhci_intr_reg - Interrupt Register Set
472 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
473 * interrupts and check for pending interrupts.
474 * @irq_control: IMOD - Interrupt Moderation Register.
475 * Used to throttle interrupts.
476 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
477 * @erst_base: ERST base address.
478 * @erst_dequeue: Event ring dequeue pointer.
479 *
480 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
481 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
482 * multiple segments of the same size. The HC places events on the ring and
483 * "updates the Cycle bit in the TRBs to indicate to software the current
484 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
485 * updates the dequeue pointer.
486 */
487 struct xhci_intr_reg {
488 __le32 irq_pending;
489 __le32 irq_control;
490 __le32 erst_size;
491 __le32 rsvd;
492 __le64 erst_base;
493 __le64 erst_dequeue;
494 };
495
496 /* irq_pending bitmasks */
497 #define ER_IRQ_PENDING(p) ((p) & 0x1)
498 /* bits 2:31 need to be preserved */
499 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
500 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
501 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
502 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
503
504 /* irq_control bitmasks */
505 /* Minimum interval between interrupts (in 250ns intervals). The interval
506 * between interrupts will be longer if there are no events on the event ring.
507 * Default is 4000 (1 ms).
508 */
509 #define ER_IRQ_INTERVAL_MASK (0xffff)
510 /* Counter used to count down the time to the next interrupt - HW use only */
511 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
512
513 /* erst_size bitmasks */
514 /* Preserve bits 16:31 of erst_size */
515 #define ERST_SIZE_MASK (0xffff << 16)
516
517 /* erst_dequeue bitmasks */
518 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
519 * where the current dequeue pointer lies. This is an optional HW hint.
520 */
521 #define ERST_DESI_MASK (0x7)
522 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
523 * a work queue (or delayed service routine)?
524 */
525 #define ERST_EHB (1 << 3)
526 #define ERST_PTR_MASK (0xf)
527
528 /**
529 * struct xhci_run_regs
530 * @microframe_index:
531 * MFINDEX - current microframe number
532 *
533 * Section 5.5 Host Controller Runtime Registers:
534 * "Software should read and write these registers using only Dword (32 bit)
535 * or larger accesses"
536 */
537 struct xhci_run_regs {
538 __le32 microframe_index;
539 __le32 rsvd[7];
540 struct xhci_intr_reg ir_set[128];
541 };
542
543 /**
544 * struct doorbell_array
545 *
546 * Bits 0 - 7: Endpoint target
547 * Bits 8 - 15: RsvdZ
548 * Bits 16 - 31: Stream ID
549 *
550 * Section 5.6
551 */
552 struct xhci_doorbell_array {
553 __le32 doorbell[256];
554 };
555
556 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
557 #define DB_VALUE_HOST 0x00000000
558
559 /**
560 * struct xhci_protocol_caps
561 * @revision: major revision, minor revision, capability ID,
562 * and next capability pointer.
563 * @name_string: Four ASCII characters to say which spec this xHC
564 * follows, typically "USB ".
565 * @port_info: Port offset, count, and protocol-defined information.
566 */
567 struct xhci_protocol_caps {
568 u32 revision;
569 u32 name_string;
570 u32 port_info;
571 };
572
573 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
574 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
575 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
576 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
577 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
578
579 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
580 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
581 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
582 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
583 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
584 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
585
586 #define PLT_MASK (0x03 << 6)
587 #define PLT_SYM (0x00 << 6)
588 #define PLT_ASYM_RX (0x02 << 6)
589 #define PLT_ASYM_TX (0x03 << 6)
590
591 /**
592 * struct xhci_container_ctx
593 * @type: Type of context. Used to calculated offsets to contained contexts.
594 * @size: Size of the context data
595 * @bytes: The raw context data given to HW
596 * @dma: dma address of the bytes
597 *
598 * Represents either a Device or Input context. Holds a pointer to the raw
599 * memory used for the context (bytes) and dma address of it (dma).
600 */
601 struct xhci_container_ctx {
602 unsigned type;
603 #define XHCI_CTX_TYPE_DEVICE 0x1
604 #define XHCI_CTX_TYPE_INPUT 0x2
605
606 int size;
607
608 u8 *bytes;
609 dma_addr_t dma;
610 };
611
612 /**
613 * struct xhci_slot_ctx
614 * @dev_info: Route string, device speed, hub info, and last valid endpoint
615 * @dev_info2: Max exit latency for device number, root hub port number
616 * @tt_info: tt_info is used to construct split transaction tokens
617 * @dev_state: slot state and device address
618 *
619 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
620 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
621 * reserved at the end of the slot context for HC internal use.
622 */
623 struct xhci_slot_ctx {
624 __le32 dev_info;
625 __le32 dev_info2;
626 __le32 tt_info;
627 __le32 dev_state;
628 /* offset 0x10 to 0x1f reserved for HC internal use */
629 __le32 reserved[4];
630 };
631
632 /* dev_info bitmasks */
633 /* Route String - 0:19 */
634 #define ROUTE_STRING_MASK (0xfffff)
635 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
636 #define DEV_SPEED (0xf << 20)
637 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
638 /* bit 24 reserved */
639 /* Is this LS/FS device connected through a HS hub? - bit 25 */
640 #define DEV_MTT (0x1 << 25)
641 /* Set if the device is a hub - bit 26 */
642 #define DEV_HUB (0x1 << 26)
643 /* Index of the last valid endpoint context in this device context - 27:31 */
644 #define LAST_CTX_MASK (0x1f << 27)
645 #define LAST_CTX(p) ((p) << 27)
646 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
647 #define SLOT_FLAG (1 << 0)
648 #define EP0_FLAG (1 << 1)
649
650 /* dev_info2 bitmasks */
651 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
652 #define MAX_EXIT (0xffff)
653 /* Root hub port number that is needed to access the USB device */
654 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
655 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
656 /* Maximum number of ports under a hub device */
657 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
658 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
659
660 /* tt_info bitmasks */
661 /*
662 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
663 * The Slot ID of the hub that isolates the high speed signaling from
664 * this low or full-speed device. '0' if attached to root hub port.
665 */
666 #define TT_SLOT (0xff)
667 /*
668 * The number of the downstream facing port of the high-speed hub
669 * '0' if the device is not low or full speed.
670 */
671 #define TT_PORT (0xff << 8)
672 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
673 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
674
675 /* dev_state bitmasks */
676 /* USB device address - assigned by the HC */
677 #define DEV_ADDR_MASK (0xff)
678 /* bits 8:26 reserved */
679 /* Slot state */
680 #define SLOT_STATE (0x1f << 27)
681 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
682
683 #define SLOT_STATE_DISABLED 0
684 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
685 #define SLOT_STATE_DEFAULT 1
686 #define SLOT_STATE_ADDRESSED 2
687 #define SLOT_STATE_CONFIGURED 3
688
689 /**
690 * struct xhci_ep_ctx
691 * @ep_info: endpoint state, streams, mult, and interval information.
692 * @ep_info2: information on endpoint type, max packet size, max burst size,
693 * error count, and whether the HC will force an event for all
694 * transactions.
695 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
696 * defines one stream, this points to the endpoint transfer ring.
697 * Otherwise, it points to a stream context array, which has a
698 * ring pointer for each flow.
699 * @tx_info:
700 * Average TRB lengths for the endpoint ring and
701 * max payload within an Endpoint Service Interval Time (ESIT).
702 *
703 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
704 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
705 * reserved at the end of the endpoint context for HC internal use.
706 */
707 struct xhci_ep_ctx {
708 __le32 ep_info;
709 __le32 ep_info2;
710 __le64 deq;
711 __le32 tx_info;
712 /* offset 0x14 - 0x1f reserved for HC internal use */
713 __le32 reserved[3];
714 };
715
716 /* ep_info bitmasks */
717 /*
718 * Endpoint State - bits 0:2
719 * 0 - disabled
720 * 1 - running
721 * 2 - halted due to halt condition - ok to manipulate endpoint ring
722 * 3 - stopped
723 * 4 - TRB error
724 * 5-7 - reserved
725 */
726 #define EP_STATE_MASK (0x7)
727 #define EP_STATE_DISABLED 0
728 #define EP_STATE_RUNNING 1
729 #define EP_STATE_HALTED 2
730 #define EP_STATE_STOPPED 3
731 #define EP_STATE_ERROR 4
732 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
733
734 /* Mult - Max number of burtst within an interval, in EP companion desc. */
735 #define EP_MULT(p) (((p) & 0x3) << 8)
736 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
737 /* bits 10:14 are Max Primary Streams */
738 /* bit 15 is Linear Stream Array */
739 /* Interval - period between requests to an endpoint - 125u increments. */
740 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
741 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
742 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
743 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
744 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
745 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
746 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
747 #define EP_HAS_LSA (1 << 15)
748 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
749 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
750
751 /* ep_info2 bitmasks */
752 /*
753 * Force Event - generate transfer events for all TRBs for this endpoint
754 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
755 */
756 #define FORCE_EVENT (0x1)
757 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
758 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
759 #define EP_TYPE(p) ((p) << 3)
760 #define ISOC_OUT_EP 1
761 #define BULK_OUT_EP 2
762 #define INT_OUT_EP 3
763 #define CTRL_EP 4
764 #define ISOC_IN_EP 5
765 #define BULK_IN_EP 6
766 #define INT_IN_EP 7
767 /* bit 6 reserved */
768 /* bit 7 is Host Initiate Disable - for disabling stream selection */
769 #define MAX_BURST(p) (((p)&0xff) << 8)
770 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
771 #define MAX_PACKET(p) (((p)&0xffff) << 16)
772 #define MAX_PACKET_MASK (0xffff << 16)
773 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
774
775 /* tx_info bitmasks */
776 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
777 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
778 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
779 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
780
781 /* deq bitmasks */
782 #define EP_CTX_CYCLE_MASK (1 << 0)
783 #define SCTX_DEQ_MASK (~0xfL)
784
785
786 /**
787 * struct xhci_input_control_context
788 * Input control context; see section 6.2.5.
789 *
790 * @drop_context: set the bit of the endpoint context you want to disable
791 * @add_context: set the bit of the endpoint context you want to enable
792 */
793 struct xhci_input_control_ctx {
794 __le32 drop_flags;
795 __le32 add_flags;
796 __le32 rsvd2[6];
797 };
798
799 #define EP_IS_ADDED(ctrl_ctx, i) \
800 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
801 #define EP_IS_DROPPED(ctrl_ctx, i) \
802 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
803
804 /* Represents everything that is needed to issue a command on the command ring.
805 * It's useful to pre-allocate these for commands that cannot fail due to
806 * out-of-memory errors, like freeing streams.
807 */
808 struct xhci_command {
809 /* Input context for changing device state */
810 struct xhci_container_ctx *in_ctx;
811 u32 status;
812 int slot_id;
813 /* If completion is null, no one is waiting on this command
814 * and the structure can be freed after the command completes.
815 */
816 struct completion *completion;
817 union xhci_trb *command_trb;
818 struct list_head cmd_list;
819
820 ANDROID_KABI_RESERVE(1);
821 ANDROID_KABI_RESERVE(2);
822 };
823
824 /* drop context bitmasks */
825 #define DROP_EP(x) (0x1 << x)
826 /* add context bitmasks */
827 #define ADD_EP(x) (0x1 << x)
828
829 struct xhci_stream_ctx {
830 /* 64-bit stream ring address, cycle state, and stream type */
831 __le64 stream_ring;
832 /* offset 0x14 - 0x1f reserved for HC internal use */
833 __le32 reserved[2];
834 };
835
836 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
837 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
838 /* Secondary stream array type, dequeue pointer is to a transfer ring */
839 #define SCT_SEC_TR 0
840 /* Primary stream array type, dequeue pointer is to a transfer ring */
841 #define SCT_PRI_TR 1
842 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
843 #define SCT_SSA_8 2
844 #define SCT_SSA_16 3
845 #define SCT_SSA_32 4
846 #define SCT_SSA_64 5
847 #define SCT_SSA_128 6
848 #define SCT_SSA_256 7
849
850 /* Assume no secondary streams for now */
851 struct xhci_stream_info {
852 struct xhci_ring **stream_rings;
853 /* Number of streams, including stream 0 (which drivers can't use) */
854 unsigned int num_streams;
855 /* The stream context array may be bigger than
856 * the number of streams the driver asked for
857 */
858 struct xhci_stream_ctx *stream_ctx_array;
859 unsigned int num_stream_ctxs;
860 dma_addr_t ctx_array_dma;
861 /* For mapping physical TRB addresses to segments in stream rings */
862 struct radix_tree_root trb_address_map;
863 struct xhci_command *free_streams_command;
864 };
865
866 #define SMALL_STREAM_ARRAY_SIZE 256
867 #define MEDIUM_STREAM_ARRAY_SIZE 1024
868
869 /* Some Intel xHCI host controllers need software to keep track of the bus
870 * bandwidth. Keep track of endpoint info here. Each root port is allocated
871 * the full bus bandwidth. We must also treat TTs (including each port under a
872 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
873 * (DMI) also limits the total bandwidth (across all domains) that can be used.
874 */
875 struct xhci_bw_info {
876 /* ep_interval is zero-based */
877 unsigned int ep_interval;
878 /* mult and num_packets are one-based */
879 unsigned int mult;
880 unsigned int num_packets;
881 unsigned int max_packet_size;
882 unsigned int max_esit_payload;
883 unsigned int type;
884 };
885
886 /* "Block" sizes in bytes the hardware uses for different device speeds.
887 * The logic in this part of the hardware limits the number of bits the hardware
888 * can use, so must represent bandwidth in a less precise manner to mimic what
889 * the scheduler hardware computes.
890 */
891 #define FS_BLOCK 1
892 #define HS_BLOCK 4
893 #define SS_BLOCK 16
894 #define DMI_BLOCK 32
895
896 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
897 * with each byte transferred. SuperSpeed devices have an initial overhead to
898 * set up bursts. These are in blocks, see above. LS overhead has already been
899 * translated into FS blocks.
900 */
901 #define DMI_OVERHEAD 8
902 #define DMI_OVERHEAD_BURST 4
903 #define SS_OVERHEAD 8
904 #define SS_OVERHEAD_BURST 32
905 #define HS_OVERHEAD 26
906 #define FS_OVERHEAD 20
907 #define LS_OVERHEAD 128
908 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
909 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
910 * of overhead associated with split transfers crossing microframe boundaries.
911 * 31 blocks is pure protocol overhead.
912 */
913 #define TT_HS_OVERHEAD (31 + 94)
914 #define TT_DMI_OVERHEAD (25 + 12)
915
916 /* Bandwidth limits in blocks */
917 #define FS_BW_LIMIT 1285
918 #define TT_BW_LIMIT 1320
919 #define HS_BW_LIMIT 1607
920 #define SS_BW_LIMIT_IN 3906
921 #define DMI_BW_LIMIT_IN 3906
922 #define SS_BW_LIMIT_OUT 3906
923 #define DMI_BW_LIMIT_OUT 3906
924
925 /* Percentage of bus bandwidth reserved for non-periodic transfers */
926 #define FS_BW_RESERVED 10
927 #define HS_BW_RESERVED 20
928 #define SS_BW_RESERVED 10
929
930 struct xhci_virt_ep {
931 struct xhci_virt_device *vdev; /* parent */
932 unsigned int ep_index;
933 struct xhci_ring *ring;
934 /* Related to endpoints that are configured to use stream IDs only */
935 struct xhci_stream_info *stream_info;
936 /* Temporary storage in case the configure endpoint command fails and we
937 * have to restore the device state to the previous state
938 */
939 struct xhci_ring *new_ring;
940 unsigned int ep_state;
941 #define SET_DEQ_PENDING (1 << 0)
942 #define EP_HALTED (1 << 1) /* For stall handling */
943 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
944 /* Transitioning the endpoint to using streams, don't enqueue URBs */
945 #define EP_GETTING_STREAMS (1 << 3)
946 #define EP_HAS_STREAMS (1 << 4)
947 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
948 #define EP_GETTING_NO_STREAMS (1 << 5)
949 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
950 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
951 /* usb_hub_clear_tt_buffer is in progress */
952 #define EP_CLEARING_TT (1 << 8)
953 /* ---- Related to URB cancellation ---- */
954 struct list_head cancelled_td_list;
955 /* Watchdog timer for stop endpoint command to cancel URBs */
956 struct timer_list stop_cmd_timer;
957 struct xhci_hcd *xhci;
958 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
959 * command. We'll need to update the ring's dequeue segment and dequeue
960 * pointer after the command completes.
961 */
962 struct xhci_segment *queued_deq_seg;
963 union xhci_trb *queued_deq_ptr;
964 /*
965 * Sometimes the xHC can not process isochronous endpoint ring quickly
966 * enough, and it will miss some isoc tds on the ring and generate
967 * a Missed Service Error Event.
968 * Set skip flag when receive a Missed Service Error Event and
969 * process the missed tds on the endpoint ring.
970 */
971 bool skip;
972 /* Bandwidth checking storage */
973 struct xhci_bw_info bw_info;
974 struct list_head bw_endpoint_list;
975 /* Isoch Frame ID checking storage */
976 int next_frame_id;
977 /* Use new Isoch TRB layout needed for extended TBC support */
978 bool use_extended_tbc;
979 };
980
981 enum xhci_overhead_type {
982 LS_OVERHEAD_TYPE = 0,
983 FS_OVERHEAD_TYPE,
984 HS_OVERHEAD_TYPE,
985 };
986
987 struct xhci_interval_bw {
988 unsigned int num_packets;
989 /* Sorted by max packet size.
990 * Head of the list is the greatest max packet size.
991 */
992 struct list_head endpoints;
993 /* How many endpoints of each speed are present. */
994 unsigned int overhead[3];
995 };
996
997 #define XHCI_MAX_INTERVAL 16
998
999 struct xhci_interval_bw_table {
1000 unsigned int interval0_esit_payload;
1001 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
1002 /* Includes reserved bandwidth for async endpoints */
1003 unsigned int bw_used;
1004 unsigned int ss_bw_in;
1005 unsigned int ss_bw_out;
1006 };
1007
1008 #define EP_CTX_PER_DEV 31
1009
1010 struct xhci_virt_device {
1011 int slot_id;
1012 struct usb_device *udev;
1013 /*
1014 * Commands to the hardware are passed an "input context" that
1015 * tells the hardware what to change in its data structures.
1016 * The hardware will return changes in an "output context" that
1017 * software must allocate for the hardware. We need to keep
1018 * track of input and output contexts separately because
1019 * these commands might fail and we don't trust the hardware.
1020 */
1021 struct xhci_container_ctx *out_ctx;
1022 /* Used for addressing devices and configuration changes */
1023 struct xhci_container_ctx *in_ctx;
1024 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1025 u8 fake_port;
1026 u8 real_port;
1027 struct xhci_interval_bw_table *bw_table;
1028 struct xhci_tt_bw_info *tt_info;
1029 /*
1030 * flags for state tracking based on events and issued commands.
1031 * Software can not rely on states from output contexts because of
1032 * latency between events and xHC updating output context values.
1033 * See xhci 1.1 section 4.8.3 for more details
1034 */
1035 unsigned long flags;
1036 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1037
1038 /* The current max exit latency for the enabled USB3 link states. */
1039 u16 current_mel;
1040 /* Used for the debugfs interfaces. */
1041 void *debugfs_private;
1042 };
1043
1044 /*
1045 * For each roothub, keep track of the bandwidth information for each periodic
1046 * interval.
1047 *
1048 * If a high speed hub is attached to the roothub, each TT associated with that
1049 * hub is a separate bandwidth domain. The interval information for the
1050 * endpoints on the devices under that TT will appear in the TT structure.
1051 */
1052 struct xhci_root_port_bw_info {
1053 struct list_head tts;
1054 unsigned int num_active_tts;
1055 struct xhci_interval_bw_table bw_table;
1056 };
1057
1058 struct xhci_tt_bw_info {
1059 struct list_head tt_list;
1060 int slot_id;
1061 int ttport;
1062 struct xhci_interval_bw_table bw_table;
1063 int active_eps;
1064 };
1065
1066
1067 /**
1068 * struct xhci_device_context_array
1069 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1070 */
1071 struct xhci_device_context_array {
1072 /* 64-bit device addresses; we only write 32-bit addresses */
1073 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1074 /* private xHCD pointers */
1075 dma_addr_t dma;
1076 };
1077 /* TODO: write function to set the 64-bit device DMA address */
1078 /*
1079 * TODO: change this to be dynamically sized at HC mem init time since the HC
1080 * might not be able to handle the maximum number of devices possible.
1081 */
1082
1083
1084 struct xhci_transfer_event {
1085 /* 64-bit buffer address, or immediate data */
1086 __le64 buffer;
1087 __le32 transfer_len;
1088 /* This field is interpreted differently based on the type of TRB */
1089 __le32 flags;
1090 };
1091
1092 /* Transfer event TRB length bit mask */
1093 /* bits 0:23 */
1094 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1095
1096 /** Transfer Event bit fields **/
1097 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1098
1099 /* Completion Code - only applicable for some types of TRBs */
1100 #define COMP_CODE_MASK (0xff << 24)
1101 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1102 #define COMP_INVALID 0
1103 #define COMP_SUCCESS 1
1104 #define COMP_DATA_BUFFER_ERROR 2
1105 #define COMP_BABBLE_DETECTED_ERROR 3
1106 #define COMP_USB_TRANSACTION_ERROR 4
1107 #define COMP_TRB_ERROR 5
1108 #define COMP_STALL_ERROR 6
1109 #define COMP_RESOURCE_ERROR 7
1110 #define COMP_BANDWIDTH_ERROR 8
1111 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1112 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1113 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1114 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1115 #define COMP_SHORT_PACKET 13
1116 #define COMP_RING_UNDERRUN 14
1117 #define COMP_RING_OVERRUN 15
1118 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1119 #define COMP_PARAMETER_ERROR 17
1120 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1121 #define COMP_CONTEXT_STATE_ERROR 19
1122 #define COMP_NO_PING_RESPONSE_ERROR 20
1123 #define COMP_EVENT_RING_FULL_ERROR 21
1124 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1125 #define COMP_MISSED_SERVICE_ERROR 23
1126 #define COMP_COMMAND_RING_STOPPED 24
1127 #define COMP_COMMAND_ABORTED 25
1128 #define COMP_STOPPED 26
1129 #define COMP_STOPPED_LENGTH_INVALID 27
1130 #define COMP_STOPPED_SHORT_PACKET 28
1131 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1132 #define COMP_ISOCH_BUFFER_OVERRUN 31
1133 #define COMP_EVENT_LOST_ERROR 32
1134 #define COMP_UNDEFINED_ERROR 33
1135 #define COMP_INVALID_STREAM_ID_ERROR 34
1136 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1137 #define COMP_SPLIT_TRANSACTION_ERROR 36
1138
xhci_trb_comp_code_string(u8 status)1139 static inline const char *xhci_trb_comp_code_string(u8 status)
1140 {
1141 switch (status) {
1142 case COMP_INVALID:
1143 return "Invalid";
1144 case COMP_SUCCESS:
1145 return "Success";
1146 case COMP_DATA_BUFFER_ERROR:
1147 return "Data Buffer Error";
1148 case COMP_BABBLE_DETECTED_ERROR:
1149 return "Babble Detected";
1150 case COMP_USB_TRANSACTION_ERROR:
1151 return "USB Transaction Error";
1152 case COMP_TRB_ERROR:
1153 return "TRB Error";
1154 case COMP_STALL_ERROR:
1155 return "Stall Error";
1156 case COMP_RESOURCE_ERROR:
1157 return "Resource Error";
1158 case COMP_BANDWIDTH_ERROR:
1159 return "Bandwidth Error";
1160 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1161 return "No Slots Available Error";
1162 case COMP_INVALID_STREAM_TYPE_ERROR:
1163 return "Invalid Stream Type Error";
1164 case COMP_SLOT_NOT_ENABLED_ERROR:
1165 return "Slot Not Enabled Error";
1166 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1167 return "Endpoint Not Enabled Error";
1168 case COMP_SHORT_PACKET:
1169 return "Short Packet";
1170 case COMP_RING_UNDERRUN:
1171 return "Ring Underrun";
1172 case COMP_RING_OVERRUN:
1173 return "Ring Overrun";
1174 case COMP_VF_EVENT_RING_FULL_ERROR:
1175 return "VF Event Ring Full Error";
1176 case COMP_PARAMETER_ERROR:
1177 return "Parameter Error";
1178 case COMP_BANDWIDTH_OVERRUN_ERROR:
1179 return "Bandwidth Overrun Error";
1180 case COMP_CONTEXT_STATE_ERROR:
1181 return "Context State Error";
1182 case COMP_NO_PING_RESPONSE_ERROR:
1183 return "No Ping Response Error";
1184 case COMP_EVENT_RING_FULL_ERROR:
1185 return "Event Ring Full Error";
1186 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1187 return "Incompatible Device Error";
1188 case COMP_MISSED_SERVICE_ERROR:
1189 return "Missed Service Error";
1190 case COMP_COMMAND_RING_STOPPED:
1191 return "Command Ring Stopped";
1192 case COMP_COMMAND_ABORTED:
1193 return "Command Aborted";
1194 case COMP_STOPPED:
1195 return "Stopped";
1196 case COMP_STOPPED_LENGTH_INVALID:
1197 return "Stopped - Length Invalid";
1198 case COMP_STOPPED_SHORT_PACKET:
1199 return "Stopped - Short Packet";
1200 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1201 return "Max Exit Latency Too Large Error";
1202 case COMP_ISOCH_BUFFER_OVERRUN:
1203 return "Isoch Buffer Overrun";
1204 case COMP_EVENT_LOST_ERROR:
1205 return "Event Lost Error";
1206 case COMP_UNDEFINED_ERROR:
1207 return "Undefined Error";
1208 case COMP_INVALID_STREAM_ID_ERROR:
1209 return "Invalid Stream ID Error";
1210 case COMP_SECONDARY_BANDWIDTH_ERROR:
1211 return "Secondary Bandwidth Error";
1212 case COMP_SPLIT_TRANSACTION_ERROR:
1213 return "Split Transaction Error";
1214 default:
1215 return "Unknown!!";
1216 }
1217 }
1218
1219 struct xhci_link_trb {
1220 /* 64-bit segment pointer*/
1221 __le64 segment_ptr;
1222 __le32 intr_target;
1223 __le32 control;
1224 };
1225
1226 /* control bitfields */
1227 #define LINK_TOGGLE (0x1<<1)
1228
1229 /* Command completion event TRB */
1230 struct xhci_event_cmd {
1231 /* Pointer to command TRB, or the value passed by the event data trb */
1232 __le64 cmd_trb;
1233 __le32 status;
1234 __le32 flags;
1235 };
1236
1237 /* flags bitmasks */
1238
1239 /* Address device - disable SetAddress */
1240 #define TRB_BSR (1<<9)
1241
1242 /* Configure Endpoint - Deconfigure */
1243 #define TRB_DC (1<<9)
1244
1245 /* Stop Ring - Transfer State Preserve */
1246 #define TRB_TSP (1<<9)
1247
1248 enum xhci_ep_reset_type {
1249 EP_HARD_RESET,
1250 EP_SOFT_RESET,
1251 };
1252
1253 /* Force Event */
1254 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1255 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1256
1257 /* Set Latency Tolerance Value */
1258 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1259
1260 /* Get Port Bandwidth */
1261 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1262
1263 /* Force Header */
1264 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1265 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1266
1267 enum xhci_setup_dev {
1268 SETUP_CONTEXT_ONLY,
1269 SETUP_CONTEXT_ADDRESS,
1270 };
1271
1272 /* bits 16:23 are the virtual function ID */
1273 /* bits 24:31 are the slot ID */
1274 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1275 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1276
1277 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1278 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1279 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1280
1281 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1282 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1283 #define LAST_EP_INDEX 30
1284
1285 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1286 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1287 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1288 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1289
1290 /* Link TRB specific fields */
1291 #define TRB_TC (1<<1)
1292
1293 /* Port Status Change Event TRB fields */
1294 /* Port ID - bits 31:24 */
1295 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1296
1297 #define EVENT_DATA (1 << 2)
1298
1299 /* Normal TRB fields */
1300 /* transfer_len bitmasks - bits 0:16 */
1301 #define TRB_LEN(p) ((p) & 0x1ffff)
1302 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1303 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1304 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1305 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1306 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1307 /* Interrupter Target - which MSI-X vector to target the completion event at */
1308 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1309 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1310 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1311 #define TRB_TBC(p) (((p) & 0x3) << 7)
1312 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1313
1314 /* Cycle bit - indicates TRB ownership by HC or HCD */
1315 #define TRB_CYCLE (1<<0)
1316 /*
1317 * Force next event data TRB to be evaluated before task switch.
1318 * Used to pass OS data back after a TD completes.
1319 */
1320 #define TRB_ENT (1<<1)
1321 /* Interrupt on short packet */
1322 #define TRB_ISP (1<<2)
1323 /* Set PCIe no snoop attribute */
1324 #define TRB_NO_SNOOP (1<<3)
1325 /* Chain multiple TRBs into a TD */
1326 #define TRB_CHAIN (1<<4)
1327 /* Interrupt on completion */
1328 #define TRB_IOC (1<<5)
1329 /* The buffer pointer contains immediate data */
1330 #define TRB_IDT (1<<6)
1331 /* TDs smaller than this might use IDT */
1332 #define TRB_IDT_MAX_SIZE 8
1333
1334 /* Block Event Interrupt */
1335 #define TRB_BEI (1<<9)
1336
1337 /* Control transfer TRB specific fields */
1338 #define TRB_DIR_IN (1<<16)
1339 #define TRB_TX_TYPE(p) ((p) << 16)
1340 #define TRB_DATA_OUT 2
1341 #define TRB_DATA_IN 3
1342
1343 /* Isochronous TRB specific fields */
1344 #define TRB_SIA (1<<31)
1345 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1346
1347 struct xhci_generic_trb {
1348 __le32 field[4];
1349 };
1350
1351 union xhci_trb {
1352 struct xhci_link_trb link;
1353 struct xhci_transfer_event trans_event;
1354 struct xhci_event_cmd event_cmd;
1355 struct xhci_generic_trb generic;
1356 };
1357
1358 /* TRB bit mask */
1359 #define TRB_TYPE_BITMASK (0xfc00)
1360 #define TRB_TYPE(p) ((p) << 10)
1361 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1362 /* TRB type IDs */
1363 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1364 #define TRB_NORMAL 1
1365 /* setup stage for control transfers */
1366 #define TRB_SETUP 2
1367 /* data stage for control transfers */
1368 #define TRB_DATA 3
1369 /* status stage for control transfers */
1370 #define TRB_STATUS 4
1371 /* isoc transfers */
1372 #define TRB_ISOC 5
1373 /* TRB for linking ring segments */
1374 #define TRB_LINK 6
1375 #define TRB_EVENT_DATA 7
1376 /* Transfer Ring No-op (not for the command ring) */
1377 #define TRB_TR_NOOP 8
1378 /* Command TRBs */
1379 /* Enable Slot Command */
1380 #define TRB_ENABLE_SLOT 9
1381 /* Disable Slot Command */
1382 #define TRB_DISABLE_SLOT 10
1383 /* Address Device Command */
1384 #define TRB_ADDR_DEV 11
1385 /* Configure Endpoint Command */
1386 #define TRB_CONFIG_EP 12
1387 /* Evaluate Context Command */
1388 #define TRB_EVAL_CONTEXT 13
1389 /* Reset Endpoint Command */
1390 #define TRB_RESET_EP 14
1391 /* Stop Transfer Ring Command */
1392 #define TRB_STOP_RING 15
1393 /* Set Transfer Ring Dequeue Pointer Command */
1394 #define TRB_SET_DEQ 16
1395 /* Reset Device Command */
1396 #define TRB_RESET_DEV 17
1397 /* Force Event Command (opt) */
1398 #define TRB_FORCE_EVENT 18
1399 /* Negotiate Bandwidth Command (opt) */
1400 #define TRB_NEG_BANDWIDTH 19
1401 /* Set Latency Tolerance Value Command (opt) */
1402 #define TRB_SET_LT 20
1403 /* Get port bandwidth Command */
1404 #define TRB_GET_BW 21
1405 /* Force Header Command - generate a transaction or link management packet */
1406 #define TRB_FORCE_HEADER 22
1407 /* No-op Command - not for transfer rings */
1408 #define TRB_CMD_NOOP 23
1409 /* TRB IDs 24-31 reserved */
1410 /* Event TRBS */
1411 /* Transfer Event */
1412 #define TRB_TRANSFER 32
1413 /* Command Completion Event */
1414 #define TRB_COMPLETION 33
1415 /* Port Status Change Event */
1416 #define TRB_PORT_STATUS 34
1417 /* Bandwidth Request Event (opt) */
1418 #define TRB_BANDWIDTH_EVENT 35
1419 /* Doorbell Event (opt) */
1420 #define TRB_DOORBELL 36
1421 /* Host Controller Event */
1422 #define TRB_HC_EVENT 37
1423 /* Device Notification Event - device sent function wake notification */
1424 #define TRB_DEV_NOTE 38
1425 /* MFINDEX Wrap Event - microframe counter wrapped */
1426 #define TRB_MFINDEX_WRAP 39
1427 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1428 #define TRB_VENDOR_DEFINED_LOW 48
1429 /* Nec vendor-specific command completion event. */
1430 #define TRB_NEC_CMD_COMP 48
1431 /* Get NEC firmware revision. */
1432 #define TRB_NEC_GET_FW 49
1433
xhci_trb_type_string(u8 type)1434 static inline const char *xhci_trb_type_string(u8 type)
1435 {
1436 switch (type) {
1437 case TRB_NORMAL:
1438 return "Normal";
1439 case TRB_SETUP:
1440 return "Setup Stage";
1441 case TRB_DATA:
1442 return "Data Stage";
1443 case TRB_STATUS:
1444 return "Status Stage";
1445 case TRB_ISOC:
1446 return "Isoch";
1447 case TRB_LINK:
1448 return "Link";
1449 case TRB_EVENT_DATA:
1450 return "Event Data";
1451 case TRB_TR_NOOP:
1452 return "No-Op";
1453 case TRB_ENABLE_SLOT:
1454 return "Enable Slot Command";
1455 case TRB_DISABLE_SLOT:
1456 return "Disable Slot Command";
1457 case TRB_ADDR_DEV:
1458 return "Address Device Command";
1459 case TRB_CONFIG_EP:
1460 return "Configure Endpoint Command";
1461 case TRB_EVAL_CONTEXT:
1462 return "Evaluate Context Command";
1463 case TRB_RESET_EP:
1464 return "Reset Endpoint Command";
1465 case TRB_STOP_RING:
1466 return "Stop Ring Command";
1467 case TRB_SET_DEQ:
1468 return "Set TR Dequeue Pointer Command";
1469 case TRB_RESET_DEV:
1470 return "Reset Device Command";
1471 case TRB_FORCE_EVENT:
1472 return "Force Event Command";
1473 case TRB_NEG_BANDWIDTH:
1474 return "Negotiate Bandwidth Command";
1475 case TRB_SET_LT:
1476 return "Set Latency Tolerance Value Command";
1477 case TRB_GET_BW:
1478 return "Get Port Bandwidth Command";
1479 case TRB_FORCE_HEADER:
1480 return "Force Header Command";
1481 case TRB_CMD_NOOP:
1482 return "No-Op Command";
1483 case TRB_TRANSFER:
1484 return "Transfer Event";
1485 case TRB_COMPLETION:
1486 return "Command Completion Event";
1487 case TRB_PORT_STATUS:
1488 return "Port Status Change Event";
1489 case TRB_BANDWIDTH_EVENT:
1490 return "Bandwidth Request Event";
1491 case TRB_DOORBELL:
1492 return "Doorbell Event";
1493 case TRB_HC_EVENT:
1494 return "Host Controller Event";
1495 case TRB_DEV_NOTE:
1496 return "Device Notification Event";
1497 case TRB_MFINDEX_WRAP:
1498 return "MFINDEX Wrap Event";
1499 case TRB_NEC_CMD_COMP:
1500 return "NEC Command Completion Event";
1501 case TRB_NEC_GET_FW:
1502 return "NET Get Firmware Revision Command";
1503 default:
1504 return "UNKNOWN";
1505 }
1506 }
1507
1508 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1509 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1510 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1511 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1512 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1513 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1514
1515 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1516 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1517
1518 /*
1519 * TRBS_PER_SEGMENT must be a multiple of 4,
1520 * since the command ring is 64-byte aligned.
1521 * It must also be greater than 16.
1522 */
1523 #define TRBS_PER_SEGMENT 256
1524 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1525 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1526 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1527 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1528 /* TRB buffer pointers can't cross 64KB boundaries */
1529 #define TRB_MAX_BUFF_SHIFT 16
1530 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1531 /* How much data is left before the 64KB boundary? */
1532 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1533 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1534 #define MAX_SOFT_RETRY 3
1535
1536 struct xhci_segment {
1537 union xhci_trb *trbs;
1538 /* private to HCD */
1539 struct xhci_segment *next;
1540 dma_addr_t dma;
1541 /* Max packet sized bounce buffer for td-fragmant alignment */
1542 dma_addr_t bounce_dma;
1543 void *bounce_buf;
1544 unsigned int bounce_offs;
1545 unsigned int bounce_len;
1546
1547 ANDROID_KABI_RESERVE(1);
1548 };
1549
1550 enum xhci_cancelled_td_status {
1551 TD_DIRTY = 0,
1552 TD_HALTED,
1553 TD_CLEARING_CACHE,
1554 TD_CLEARED,
1555 };
1556
1557 struct xhci_td {
1558 struct list_head td_list;
1559 struct list_head cancelled_td_list;
1560 int status;
1561 enum xhci_cancelled_td_status cancel_status;
1562 struct urb *urb;
1563 struct xhci_segment *start_seg;
1564 union xhci_trb *first_trb;
1565 union xhci_trb *last_trb;
1566 struct xhci_segment *last_trb_seg;
1567 struct xhci_segment *bounce_seg;
1568 /* actual_length of the URB has already been set */
1569 bool urb_length_set;
1570 bool error_mid_td;
1571 unsigned int num_trbs;
1572 };
1573
1574 /* xHCI command default timeout value */
1575 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1576
1577 /* command descriptor */
1578 struct xhci_cd {
1579 struct xhci_command *command;
1580 union xhci_trb *cmd_trb;
1581 };
1582
1583 enum xhci_ring_type {
1584 TYPE_CTRL = 0,
1585 TYPE_ISOC,
1586 TYPE_BULK,
1587 TYPE_INTR,
1588 TYPE_STREAM,
1589 TYPE_COMMAND,
1590 TYPE_EVENT,
1591 };
1592
xhci_ring_type_string(enum xhci_ring_type type)1593 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1594 {
1595 switch (type) {
1596 case TYPE_CTRL:
1597 return "CTRL";
1598 case TYPE_ISOC:
1599 return "ISOC";
1600 case TYPE_BULK:
1601 return "BULK";
1602 case TYPE_INTR:
1603 return "INTR";
1604 case TYPE_STREAM:
1605 return "STREAM";
1606 case TYPE_COMMAND:
1607 return "CMD";
1608 case TYPE_EVENT:
1609 return "EVENT";
1610 }
1611
1612 return "UNKNOWN";
1613 }
1614
1615 struct xhci_ring {
1616 struct xhci_segment *first_seg;
1617 struct xhci_segment *last_seg;
1618 union xhci_trb *enqueue;
1619 struct xhci_segment *enq_seg;
1620 union xhci_trb *dequeue;
1621 struct xhci_segment *deq_seg;
1622 struct list_head td_list;
1623 /*
1624 * Write the cycle state into the TRB cycle field to give ownership of
1625 * the TRB to the host controller (if we are the producer), or to check
1626 * if we own the TRB (if we are the consumer). See section 4.9.1.
1627 */
1628 u32 cycle_state;
1629 unsigned int err_count;
1630 unsigned int stream_id;
1631 unsigned int num_segs;
1632 unsigned int num_trbs_free;
1633 unsigned int num_trbs_free_temp;
1634 unsigned int bounce_buf_len;
1635 enum xhci_ring_type type;
1636 bool last_td_was_short;
1637 struct radix_tree_root *trb_address_map;
1638
1639 ANDROID_KABI_RESERVE(1);
1640 ANDROID_KABI_RESERVE(2);
1641 };
1642
1643 struct xhci_erst_entry {
1644 /* 64-bit event ring segment address */
1645 __le64 seg_addr;
1646 __le32 seg_size;
1647 /* Set to zero */
1648 __le32 rsvd;
1649 };
1650
1651 struct xhci_erst {
1652 struct xhci_erst_entry *entries;
1653 unsigned int num_entries;
1654 /* xhci->event_ring keeps track of segment dma addresses */
1655 dma_addr_t erst_dma_addr;
1656 /* Num entries the ERST can contain */
1657 unsigned int erst_size;
1658
1659 ANDROID_KABI_RESERVE(1);
1660 };
1661
1662 struct xhci_scratchpad {
1663 u64 *sp_array;
1664 dma_addr_t sp_dma;
1665 void **sp_buffers;
1666 };
1667
1668 struct urb_priv {
1669 int num_tds;
1670 int num_tds_done;
1671 struct xhci_td td[];
1672 };
1673
1674 /*
1675 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1676 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1677 * meaning 64 ring segments.
1678 * Initial allocated size of the ERST, in number of entries */
1679 #define ERST_NUM_SEGS 1
1680 /* Initial allocated size of the ERST, in number of entries */
1681 #define ERST_SIZE 64
1682 /* Initial number of event segment rings allocated */
1683 #define ERST_ENTRIES 1
1684 /* Poll every 60 seconds */
1685 #define POLL_TIMEOUT 60
1686 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1687 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1688 /* XXX: Make these module parameters */
1689
1690 struct s3_save {
1691 u32 command;
1692 u32 dev_nt;
1693 u64 dcbaa_ptr;
1694 u32 config_reg;
1695 u32 irq_pending;
1696 u32 irq_control;
1697 u32 erst_size;
1698 u64 erst_base;
1699 u64 erst_dequeue;
1700 };
1701
1702 /* Use for lpm */
1703 struct dev_info {
1704 u32 dev_id;
1705 struct list_head list;
1706 };
1707
1708 struct xhci_bus_state {
1709 unsigned long bus_suspended;
1710 unsigned long next_statechange;
1711
1712 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1713 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1714 u32 port_c_suspend;
1715 u32 suspended_ports;
1716 u32 port_remote_wakeup;
1717 unsigned long resume_done[USB_MAXCHILDREN];
1718 /* which ports have started to resume */
1719 unsigned long resuming_ports;
1720 /* Which ports are waiting on RExit to U0 transition. */
1721 unsigned long rexit_ports;
1722 struct completion rexit_done[USB_MAXCHILDREN];
1723 struct completion u3exit_done[USB_MAXCHILDREN];
1724 };
1725
1726
1727 /*
1728 * It can take up to 20 ms to transition from RExit to U0 on the
1729 * Intel Lynx Point LP xHCI host.
1730 */
1731 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1732 struct xhci_port_cap {
1733 u32 *psi; /* array of protocol speed ID entries */
1734 u8 psi_count;
1735 u8 psi_uid_count;
1736 u8 maj_rev;
1737 u8 min_rev;
1738 };
1739
1740 struct xhci_port {
1741 __le32 __iomem *addr;
1742 int hw_portnum;
1743 int hcd_portnum;
1744 struct xhci_hub *rhub;
1745 struct xhci_port_cap *port_cap;
1746 };
1747
1748 struct xhci_hub {
1749 struct xhci_port **ports;
1750 unsigned int num_ports;
1751 struct usb_hcd *hcd;
1752 /* keep track of bus suspend info */
1753 struct xhci_bus_state bus_state;
1754 /* supported prococol extended capabiliy values */
1755 u8 maj_rev;
1756 u8 min_rev;
1757 };
1758
1759 /* There is one xhci_hcd structure per controller */
1760 struct xhci_hcd {
1761 struct usb_hcd *main_hcd;
1762 struct usb_hcd *shared_hcd;
1763 /* glue to PCI and HCD framework */
1764 struct xhci_cap_regs __iomem *cap_regs;
1765 struct xhci_op_regs __iomem *op_regs;
1766 struct xhci_run_regs __iomem *run_regs;
1767 struct xhci_doorbell_array __iomem *dba;
1768 /* Our HCD's current interrupter register set */
1769 struct xhci_intr_reg __iomem *ir_set;
1770
1771 /* Cached register copies of read-only HC data */
1772 __u32 hcs_params1;
1773 __u32 hcs_params2;
1774 __u32 hcs_params3;
1775 __u32 hcc_params;
1776 __u32 hcc_params2;
1777
1778 spinlock_t lock;
1779
1780 /* packed release number */
1781 u8 sbrn;
1782 u16 hci_version;
1783 u8 max_slots;
1784 u8 max_interrupters;
1785 u8 max_ports;
1786 u8 isoc_threshold;
1787 /* imod_interval in ns (I * 250ns) */
1788 u32 imod_interval;
1789 int event_ring_max;
1790 /* 4KB min, 128MB max */
1791 int page_size;
1792 /* Valid values are 12 to 20, inclusive */
1793 int page_shift;
1794 /* msi-x vectors */
1795 int msix_count;
1796 /* optional clocks */
1797 struct clk *clk;
1798 struct clk *reg_clk;
1799 /* optional reset controller */
1800 struct reset_control *reset;
1801 /* data structures */
1802 struct xhci_device_context_array *dcbaa;
1803 struct xhci_ring *cmd_ring;
1804 unsigned int cmd_ring_state;
1805 #define CMD_RING_STATE_RUNNING (1 << 0)
1806 #define CMD_RING_STATE_ABORTED (1 << 1)
1807 #define CMD_RING_STATE_STOPPED (1 << 2)
1808 struct list_head cmd_list;
1809 unsigned int cmd_ring_reserved_trbs;
1810 struct delayed_work cmd_timer;
1811 struct completion cmd_ring_stop_completion;
1812 struct xhci_command *current_cmd;
1813 struct xhci_ring *event_ring;
1814 struct xhci_erst erst;
1815 /* Scratchpad */
1816 struct xhci_scratchpad *scratchpad;
1817 /* Store LPM test failed devices' information */
1818 struct list_head lpm_failed_devs;
1819
1820 /* slot enabling and address device helpers */
1821 /* these are not thread safe so use mutex */
1822 struct mutex mutex;
1823 /* For USB 3.0 LPM enable/disable. */
1824 struct xhci_command *lpm_command;
1825 /* Internal mirror of the HW's dcbaa */
1826 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1827 /* For keeping track of bandwidth domains per roothub. */
1828 struct xhci_root_port_bw_info *rh_bw;
1829
1830 /* DMA pools */
1831 struct dma_pool *device_pool;
1832 struct dma_pool *segment_pool;
1833 struct dma_pool *small_streams_pool;
1834 struct dma_pool *medium_streams_pool;
1835
1836 /* Host controller watchdog timer structures */
1837 unsigned int xhc_state;
1838
1839 u32 command;
1840 struct s3_save s3;
1841 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1842 *
1843 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1844 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1845 * that sees this status (other than the timer that set it) should stop touching
1846 * hardware immediately. Interrupt handlers should return immediately when
1847 * they see this status (any time they drop and re-acquire xhci->lock).
1848 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1849 * putting the TD on the canceled list, etc.
1850 *
1851 * There are no reports of xHCI host controllers that display this issue.
1852 */
1853 #define XHCI_STATE_DYING (1 << 0)
1854 #define XHCI_STATE_HALTED (1 << 1)
1855 #define XHCI_STATE_REMOVING (1 << 2)
1856 unsigned long long quirks;
1857 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1858 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1859 #define XHCI_NEC_HOST BIT_ULL(2)
1860 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1861 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1862 /*
1863 * Certain Intel host controllers have a limit to the number of endpoint
1864 * contexts they can handle. Ideally, they would signal that they can't handle
1865 * anymore endpoint contexts by returning a Resource Error for the Configure
1866 * Endpoint command, but they don't. Instead they expect software to keep track
1867 * of the number of active endpoints for them, across configure endpoint
1868 * commands, reset device commands, disable slot commands, and address device
1869 * commands.
1870 */
1871 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1872 #define XHCI_BROKEN_MSI BIT_ULL(6)
1873 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1874 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1875 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1876 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1877 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1878 #define XHCI_INTEL_HOST BIT_ULL(12)
1879 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1880 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1881 #define XHCI_AVOID_BEI BIT_ULL(15)
1882 #define XHCI_PLAT BIT_ULL(16)
1883 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1884 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1885 /* For controllers with a broken beyond repair streams implementation */
1886 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1887 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1888 #define XHCI_MTK_HOST BIT_ULL(21)
1889 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1890 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1891 #define XHCI_MISSING_CAS BIT_ULL(24)
1892 /* For controller with a broken Port Disable implementation */
1893 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1894 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1895 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1896 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1897 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1898 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1899 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1900 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1901 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1902 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1903 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1904 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1905 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1906 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1907 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1908 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1909 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1910 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1911 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1912 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1913 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1914
1915 unsigned int num_active_eps;
1916 unsigned int limit_active_eps;
1917 struct xhci_port *hw_ports;
1918 struct xhci_hub usb2_rhub;
1919 struct xhci_hub usb3_rhub;
1920 /* support xHCI 1.0 spec USB2 hardware LPM */
1921 unsigned hw_lpm_support:1;
1922 /* Broken Suspend flag for SNPS Suspend resume issue */
1923 unsigned broken_suspend:1;
1924 /* cached usb2 extened protocol capabilites */
1925 u32 *ext_caps;
1926 unsigned int num_ext_caps;
1927 /* cached extended protocol port capabilities */
1928 struct xhci_port_cap *port_caps;
1929 unsigned int num_port_caps;
1930 /* Compliance Mode Recovery Data */
1931 struct timer_list comp_mode_recovery_timer;
1932 u32 port_status_u0;
1933 u16 test_mode;
1934 /* Compliance Mode Timer Triggered every 2 seconds */
1935 #define COMP_MODE_RCVRY_MSECS 2000
1936
1937 struct dentry *debugfs_root;
1938 struct dentry *debugfs_slots;
1939 struct list_head regset_list;
1940
1941 void *dbc;
1942
1943 /* Used for bug 194461020 */
1944 ANDROID_KABI_USE(1, struct xhci_vendor_ops *vendor_ops);
1945
1946 ANDROID_KABI_RESERVE(2);
1947 ANDROID_KABI_RESERVE(3);
1948 ANDROID_KABI_RESERVE(4);
1949
1950 /* platform-specific data -- must come last */
1951 unsigned long priv[] __aligned(sizeof(s64));
1952 };
1953
1954 /* Platform specific overrides to generic XHCI hc_driver ops */
1955 struct xhci_driver_overrides {
1956 size_t extra_priv_size;
1957 int (*reset)(struct usb_hcd *hcd);
1958 int (*start)(struct usb_hcd *hcd);
1959 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1960 struct usb_host_endpoint *ep);
1961 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1962 struct usb_host_endpoint *ep);
1963 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1964 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1965 int (*address_device)(struct usb_hcd *hcd, struct usb_device *udev);
1966 int (*bus_suspend)(struct usb_hcd *hcd);
1967 int (*bus_resume)(struct usb_hcd *hcd);
1968 };
1969
1970 #define XHCI_CFC_DELAY 10
1971
1972 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1973 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1974 {
1975 struct usb_hcd *primary_hcd;
1976
1977 if (usb_hcd_is_primary_hcd(hcd))
1978 primary_hcd = hcd;
1979 else
1980 primary_hcd = hcd->primary_hcd;
1981
1982 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1983 }
1984
xhci_to_hcd(struct xhci_hcd * xhci)1985 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1986 {
1987 return xhci->main_hcd;
1988 }
1989
1990 #define xhci_dbg(xhci, fmt, args...) \
1991 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1992 #define xhci_err(xhci, fmt, args...) \
1993 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1994 #define xhci_warn(xhci, fmt, args...) \
1995 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1996 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1997 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1998 #define xhci_info(xhci, fmt, args...) \
1999 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2000
2001 /*
2002 * Registers should always be accessed with double word or quad word accesses.
2003 *
2004 * Some xHCI implementations may support 64-bit address pointers. Registers
2005 * with 64-bit address pointers should be written to with dword accesses by
2006 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
2007 * xHCI implementations that do not support 64-bit address pointers will ignore
2008 * the high dword, and write order is irrelevant.
2009 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)2010 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2011 __le64 __iomem *regs)
2012 {
2013 return lo_hi_readq(regs);
2014 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)2015 static inline void xhci_write_64(struct xhci_hcd *xhci,
2016 const u64 val, __le64 __iomem *regs)
2017 {
2018 lo_hi_writeq(val, regs);
2019 }
2020
xhci_link_trb_quirk(struct xhci_hcd * xhci)2021 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2022 {
2023 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2024 }
2025
2026 /* xHCI debugging */
2027 char *xhci_get_slot_state(struct xhci_hcd *xhci,
2028 struct xhci_container_ctx *ctx);
2029 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2030 const char *fmt, ...);
2031
2032 /* xHCI memory management */
2033 void xhci_mem_cleanup(struct xhci_hcd *xhci);
2034 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2035 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2036 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2037 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2038 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2039 struct usb_device *udev);
2040 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2041 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
2042 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2043 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2044 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2045 struct xhci_virt_device *virt_dev,
2046 int old_active_eps);
2047 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2048 void xhci_update_bw_info(struct xhci_hcd *xhci,
2049 struct xhci_container_ctx *in_ctx,
2050 struct xhci_input_control_ctx *ctrl_ctx,
2051 struct xhci_virt_device *virt_dev);
2052 void xhci_endpoint_copy(struct xhci_hcd *xhci,
2053 struct xhci_container_ctx *in_ctx,
2054 struct xhci_container_ctx *out_ctx,
2055 unsigned int ep_index);
2056 void xhci_slot_copy(struct xhci_hcd *xhci,
2057 struct xhci_container_ctx *in_ctx,
2058 struct xhci_container_ctx *out_ctx);
2059 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2060 struct usb_device *udev, struct usb_host_endpoint *ep,
2061 gfp_t mem_flags);
2062 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2063 unsigned int num_segs, unsigned int cycle_state,
2064 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2065 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2066 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2067 unsigned int num_trbs, gfp_t flags);
2068 int xhci_alloc_erst(struct xhci_hcd *xhci,
2069 struct xhci_ring *evt_ring,
2070 struct xhci_erst *erst,
2071 gfp_t flags);
2072 void xhci_initialize_ring_info(struct xhci_ring *ring,
2073 unsigned int cycle_state);
2074 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2075 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2076 struct xhci_virt_device *virt_dev,
2077 unsigned int ep_index);
2078 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2079 unsigned int num_stream_ctxs,
2080 unsigned int num_streams,
2081 unsigned int max_packet, gfp_t flags);
2082 void xhci_free_stream_info(struct xhci_hcd *xhci,
2083 struct xhci_stream_info *stream_info);
2084 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2085 struct xhci_ep_ctx *ep_ctx,
2086 struct xhci_stream_info *stream_info);
2087 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2088 struct xhci_virt_ep *ep);
2089 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2090 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2091 struct xhci_ring *xhci_dma_to_transfer_ring(
2092 struct xhci_virt_ep *ep,
2093 u64 address);
2094 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2095 bool allocate_completion, gfp_t mem_flags);
2096 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2097 bool allocate_completion, gfp_t mem_flags);
2098 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2099 void xhci_free_command(struct xhci_hcd *xhci,
2100 struct xhci_command *command);
2101 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2102 int type, gfp_t flags);
2103 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2104 struct xhci_container_ctx *ctx);
2105
2106 /* xHCI host controller glue */
2107 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2108 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2109 void xhci_quiesce(struct xhci_hcd *xhci);
2110 int xhci_halt(struct xhci_hcd *xhci);
2111 int xhci_start(struct xhci_hcd *xhci);
2112 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2113 int xhci_run(struct usb_hcd *hcd);
2114 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2115 void xhci_shutdown(struct usb_hcd *hcd);
2116 void xhci_init_driver(struct hc_driver *drv,
2117 const struct xhci_driver_overrides *over);
2118 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2119 struct usb_host_endpoint *ep);
2120 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2121 struct usb_host_endpoint *ep);
2122 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2123 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2124 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
2125 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2126 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2127
2128 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2129 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2130
2131 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2132 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2133 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2134 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2135 struct xhci_virt_device *virt_dev,
2136 struct usb_device *hdev,
2137 struct usb_tt *tt, gfp_t mem_flags);
2138
2139 /* xHCI ring, segment, TRB, and TD functions */
2140 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2141 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2142 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2143 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2144 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2145 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2146 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2147 u32 trb_type, u32 slot_id);
2148 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2149 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2150 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2151 u32 field1, u32 field2, u32 field3, u32 field4);
2152 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2153 int slot_id, unsigned int ep_index, int suspend);
2154 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2155 int slot_id, unsigned int ep_index);
2156 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2157 int slot_id, unsigned int ep_index);
2158 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2159 int slot_id, unsigned int ep_index);
2160 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2161 struct urb *urb, int slot_id, unsigned int ep_index);
2162 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2163 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2164 bool command_must_succeed);
2165 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2166 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2167 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2168 int slot_id, unsigned int ep_index,
2169 enum xhci_ep_reset_type reset_type);
2170 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2171 u32 slot_id);
2172 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2173 unsigned int ep_index, unsigned int stream_id,
2174 struct xhci_td *td);
2175 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2176 void xhci_handle_command_timeout(struct work_struct *work);
2177
2178 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2179 unsigned int ep_index, unsigned int stream_id);
2180 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2181 unsigned int slot_id,
2182 unsigned int ep_index);
2183 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2184 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2185 unsigned int count_trbs(u64 addr, u64 len);
2186
2187 /* xHCI roothub code */
2188 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2189 u32 link_state);
2190 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2191 u32 port_bit);
2192 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2193 char *buf, u16 wLength);
2194 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2195 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2196 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2197
2198 void xhci_hc_died(struct xhci_hcd *xhci);
2199
2200 #ifdef CONFIG_PM
2201 int xhci_bus_suspend(struct usb_hcd *hcd);
2202 int xhci_bus_resume(struct usb_hcd *hcd);
2203 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2204 #else
2205 #define xhci_bus_suspend NULL
2206 #define xhci_bus_resume NULL
2207 #define xhci_get_resuming_ports NULL
2208 #endif /* CONFIG_PM */
2209
2210 u32 xhci_port_state_to_neutral(u32 state);
2211 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2212 u16 port);
2213 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2214
2215 /* xHCI contexts */
2216 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2217 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2218 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2219
2220 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2221 unsigned int slot_id, unsigned int ep_index,
2222 unsigned int stream_id);
2223
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)2224 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2225 struct urb *urb)
2226 {
2227 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2228 xhci_get_endpoint_index(&urb->ep->desc),
2229 urb->stream_id);
2230 }
2231
2232 /**
2233 * struct xhci_vendor_ops - function callbacks for vendor specific operations
2234 * @vendor_init: called for vendor init process
2235 * @vendor_cleanup: called for vendor cleanup process
2236 * @is_usb_offload_enabled: called to check if usb offload enabled
2237 * @queue_irq_work: called to queue vendor specific irq work
2238 * @alloc_dcbaa: called when allocating vendor specific dcbaa
2239 * @free_dcbaa: called to free vendor specific dcbaa
2240 * @alloc_transfer_ring: called when remote transfer ring allocation is required
2241 * @free_transfer_ring: called to free vendor specific transfer ring
2242 * @sync_dev_ctx: called when synchronization for device context is required
2243 * @alloc_container_ctx: called when allocating vendor specific container context
2244 * @free_container_ctx: called to free vendor specific container context
2245 */
2246 struct xhci_vendor_ops {
2247 int (*vendor_init)(struct xhci_hcd *xhci);
2248 void (*vendor_cleanup)(struct xhci_hcd *xhci);
2249 bool (*is_usb_offload_enabled)(struct xhci_hcd *xhci,
2250 struct xhci_virt_device *vdev,
2251 unsigned int ep_index);
2252 irqreturn_t (*queue_irq_work)(struct xhci_hcd *xhci);
2253
2254 struct xhci_device_context_array *(*alloc_dcbaa)(struct xhci_hcd *xhci,
2255 gfp_t flags);
2256 void (*free_dcbaa)(struct xhci_hcd *xhci);
2257
2258 struct xhci_ring *(*alloc_transfer_ring)(struct xhci_hcd *xhci,
2259 u32 endpoint_type, enum xhci_ring_type ring_type,
2260 unsigned int max_packet, gfp_t mem_flags);
2261 void (*free_transfer_ring)(struct xhci_hcd *xhci,
2262 struct xhci_virt_device *virt_dev, unsigned int ep_index);
2263 int (*sync_dev_ctx)(struct xhci_hcd *xhci, unsigned int slot_id);
2264 bool (*usb_offload_skip_urb)(struct xhci_hcd *xhci, struct urb *urb);
2265 void (*alloc_container_ctx)(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx,
2266 int type, gfp_t flags);
2267 void (*free_container_ctx)(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2268 };
2269
2270 struct xhci_vendor_ops *xhci_vendor_get_ops(struct xhci_hcd *xhci);
2271
2272 int xhci_vendor_sync_dev_ctx(struct xhci_hcd *xhci, unsigned int slot_id);
2273 bool xhci_vendor_usb_offload_skip_urb(struct xhci_hcd *xhci, struct urb *urb);
2274 void xhci_vendor_free_transfer_ring(struct xhci_hcd *xhci,
2275 struct xhci_virt_device *virt_dev, unsigned int ep_index);
2276 bool xhci_vendor_is_usb_offload_enabled(struct xhci_hcd *xhci,
2277 struct xhci_virt_device *virt_dev, unsigned int ep_index);
2278
2279 /*
2280 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2281 * them anyways as we where unable to find a device that matches the
2282 * constraints.
2283 */
xhci_urb_suitable_for_idt(struct urb * urb)2284 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2285 {
2286 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2287 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2288 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2289 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2290 !urb->num_sgs)
2291 return true;
2292
2293 return false;
2294 }
2295
xhci_slot_state_string(u32 state)2296 static inline char *xhci_slot_state_string(u32 state)
2297 {
2298 switch (state) {
2299 case SLOT_STATE_ENABLED:
2300 return "enabled/disabled";
2301 case SLOT_STATE_DEFAULT:
2302 return "default";
2303 case SLOT_STATE_ADDRESSED:
2304 return "addressed";
2305 case SLOT_STATE_CONFIGURED:
2306 return "configured";
2307 default:
2308 return "reserved";
2309 }
2310 }
2311
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)2312 static inline const char *xhci_decode_trb(char *str, size_t size,
2313 u32 field0, u32 field1, u32 field2, u32 field3)
2314 {
2315 int type = TRB_FIELD_TO_TYPE(field3);
2316
2317 switch (type) {
2318 case TRB_LINK:
2319 snprintf(str, size,
2320 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2321 field1, field0, GET_INTR_TARGET(field2),
2322 xhci_trb_type_string(type),
2323 field3 & TRB_IOC ? 'I' : 'i',
2324 field3 & TRB_CHAIN ? 'C' : 'c',
2325 field3 & TRB_TC ? 'T' : 't',
2326 field3 & TRB_CYCLE ? 'C' : 'c');
2327 break;
2328 case TRB_TRANSFER:
2329 case TRB_COMPLETION:
2330 case TRB_PORT_STATUS:
2331 case TRB_BANDWIDTH_EVENT:
2332 case TRB_DOORBELL:
2333 case TRB_HC_EVENT:
2334 case TRB_DEV_NOTE:
2335 case TRB_MFINDEX_WRAP:
2336 snprintf(str, size,
2337 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2338 field1, field0,
2339 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2340 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2341 /* Macro decrements 1, maybe it shouldn't?!? */
2342 TRB_TO_EP_INDEX(field3) + 1,
2343 xhci_trb_type_string(type),
2344 field3 & EVENT_DATA ? 'E' : 'e',
2345 field3 & TRB_CYCLE ? 'C' : 'c');
2346
2347 break;
2348 case TRB_SETUP:
2349 snprintf(str, size,
2350 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2351 field0 & 0xff,
2352 (field0 & 0xff00) >> 8,
2353 (field0 & 0xff000000) >> 24,
2354 (field0 & 0xff0000) >> 16,
2355 (field1 & 0xff00) >> 8,
2356 field1 & 0xff,
2357 (field1 & 0xff000000) >> 16 |
2358 (field1 & 0xff0000) >> 16,
2359 TRB_LEN(field2), GET_TD_SIZE(field2),
2360 GET_INTR_TARGET(field2),
2361 xhci_trb_type_string(type),
2362 field3 & TRB_IDT ? 'I' : 'i',
2363 field3 & TRB_IOC ? 'I' : 'i',
2364 field3 & TRB_CYCLE ? 'C' : 'c');
2365 break;
2366 case TRB_DATA:
2367 snprintf(str, size,
2368 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2369 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2370 GET_INTR_TARGET(field2),
2371 xhci_trb_type_string(type),
2372 field3 & TRB_IDT ? 'I' : 'i',
2373 field3 & TRB_IOC ? 'I' : 'i',
2374 field3 & TRB_CHAIN ? 'C' : 'c',
2375 field3 & TRB_NO_SNOOP ? 'S' : 's',
2376 field3 & TRB_ISP ? 'I' : 'i',
2377 field3 & TRB_ENT ? 'E' : 'e',
2378 field3 & TRB_CYCLE ? 'C' : 'c');
2379 break;
2380 case TRB_STATUS:
2381 snprintf(str, size,
2382 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2383 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2384 GET_INTR_TARGET(field2),
2385 xhci_trb_type_string(type),
2386 field3 & TRB_IOC ? 'I' : 'i',
2387 field3 & TRB_CHAIN ? 'C' : 'c',
2388 field3 & TRB_ENT ? 'E' : 'e',
2389 field3 & TRB_CYCLE ? 'C' : 'c');
2390 break;
2391 case TRB_NORMAL:
2392 case TRB_ISOC:
2393 case TRB_EVENT_DATA:
2394 case TRB_TR_NOOP:
2395 snprintf(str, size,
2396 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2397 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2398 GET_INTR_TARGET(field2),
2399 xhci_trb_type_string(type),
2400 field3 & TRB_BEI ? 'B' : 'b',
2401 field3 & TRB_IDT ? 'I' : 'i',
2402 field3 & TRB_IOC ? 'I' : 'i',
2403 field3 & TRB_CHAIN ? 'C' : 'c',
2404 field3 & TRB_NO_SNOOP ? 'S' : 's',
2405 field3 & TRB_ISP ? 'I' : 'i',
2406 field3 & TRB_ENT ? 'E' : 'e',
2407 field3 & TRB_CYCLE ? 'C' : 'c');
2408 break;
2409
2410 case TRB_CMD_NOOP:
2411 case TRB_ENABLE_SLOT:
2412 snprintf(str, size,
2413 "%s: flags %c",
2414 xhci_trb_type_string(type),
2415 field3 & TRB_CYCLE ? 'C' : 'c');
2416 break;
2417 case TRB_DISABLE_SLOT:
2418 case TRB_NEG_BANDWIDTH:
2419 snprintf(str, size,
2420 "%s: slot %d flags %c",
2421 xhci_trb_type_string(type),
2422 TRB_TO_SLOT_ID(field3),
2423 field3 & TRB_CYCLE ? 'C' : 'c');
2424 break;
2425 case TRB_ADDR_DEV:
2426 snprintf(str, size,
2427 "%s: ctx %08x%08x slot %d flags %c:%c",
2428 xhci_trb_type_string(type),
2429 field1, field0,
2430 TRB_TO_SLOT_ID(field3),
2431 field3 & TRB_BSR ? 'B' : 'b',
2432 field3 & TRB_CYCLE ? 'C' : 'c');
2433 break;
2434 case TRB_CONFIG_EP:
2435 snprintf(str, size,
2436 "%s: ctx %08x%08x slot %d flags %c:%c",
2437 xhci_trb_type_string(type),
2438 field1, field0,
2439 TRB_TO_SLOT_ID(field3),
2440 field3 & TRB_DC ? 'D' : 'd',
2441 field3 & TRB_CYCLE ? 'C' : 'c');
2442 break;
2443 case TRB_EVAL_CONTEXT:
2444 snprintf(str, size,
2445 "%s: ctx %08x%08x slot %d flags %c",
2446 xhci_trb_type_string(type),
2447 field1, field0,
2448 TRB_TO_SLOT_ID(field3),
2449 field3 & TRB_CYCLE ? 'C' : 'c');
2450 break;
2451 case TRB_RESET_EP:
2452 snprintf(str, size,
2453 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2454 xhci_trb_type_string(type),
2455 field1, field0,
2456 TRB_TO_SLOT_ID(field3),
2457 /* Macro decrements 1, maybe it shouldn't?!? */
2458 TRB_TO_EP_INDEX(field3) + 1,
2459 field3 & TRB_TSP ? 'T' : 't',
2460 field3 & TRB_CYCLE ? 'C' : 'c');
2461 break;
2462 case TRB_STOP_RING:
2463 snprintf(str, size,
2464 "%s: slot %d sp %d ep %d flags %c",
2465 xhci_trb_type_string(type),
2466 TRB_TO_SLOT_ID(field3),
2467 TRB_TO_SUSPEND_PORT(field3),
2468 /* Macro decrements 1, maybe it shouldn't?!? */
2469 TRB_TO_EP_INDEX(field3) + 1,
2470 field3 & TRB_CYCLE ? 'C' : 'c');
2471 break;
2472 case TRB_SET_DEQ:
2473 snprintf(str, size,
2474 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2475 xhci_trb_type_string(type),
2476 field1, field0,
2477 TRB_TO_STREAM_ID(field2),
2478 TRB_TO_SLOT_ID(field3),
2479 /* Macro decrements 1, maybe it shouldn't?!? */
2480 TRB_TO_EP_INDEX(field3) + 1,
2481 field3 & TRB_CYCLE ? 'C' : 'c');
2482 break;
2483 case TRB_RESET_DEV:
2484 snprintf(str, size,
2485 "%s: slot %d flags %c",
2486 xhci_trb_type_string(type),
2487 TRB_TO_SLOT_ID(field3),
2488 field3 & TRB_CYCLE ? 'C' : 'c');
2489 break;
2490 case TRB_FORCE_EVENT:
2491 snprintf(str, size,
2492 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2493 xhci_trb_type_string(type),
2494 field1, field0,
2495 TRB_TO_VF_INTR_TARGET(field2),
2496 TRB_TO_VF_ID(field3),
2497 field3 & TRB_CYCLE ? 'C' : 'c');
2498 break;
2499 case TRB_SET_LT:
2500 snprintf(str, size,
2501 "%s: belt %d flags %c",
2502 xhci_trb_type_string(type),
2503 TRB_TO_BELT(field3),
2504 field3 & TRB_CYCLE ? 'C' : 'c');
2505 break;
2506 case TRB_GET_BW:
2507 snprintf(str, size,
2508 "%s: ctx %08x%08x slot %d speed %d flags %c",
2509 xhci_trb_type_string(type),
2510 field1, field0,
2511 TRB_TO_SLOT_ID(field3),
2512 TRB_TO_DEV_SPEED(field3),
2513 field3 & TRB_CYCLE ? 'C' : 'c');
2514 break;
2515 case TRB_FORCE_HEADER:
2516 snprintf(str, size,
2517 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2518 xhci_trb_type_string(type),
2519 field2, field1, field0 & 0xffffffe0,
2520 TRB_TO_PACKET_TYPE(field0),
2521 TRB_TO_ROOTHUB_PORT(field3),
2522 field3 & TRB_CYCLE ? 'C' : 'c');
2523 break;
2524 default:
2525 snprintf(str, size,
2526 "type '%s' -> raw %08x %08x %08x %08x",
2527 xhci_trb_type_string(type),
2528 field0, field1, field2, field3);
2529 }
2530
2531 return str;
2532 }
2533
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2534 static inline const char *xhci_decode_ctrl_ctx(char *str,
2535 unsigned long drop, unsigned long add)
2536 {
2537 unsigned int bit;
2538 int ret = 0;
2539
2540 str[0] = '\0';
2541
2542 if (drop) {
2543 ret = sprintf(str, "Drop:");
2544 for_each_set_bit(bit, &drop, 32)
2545 ret += sprintf(str + ret, " %d%s",
2546 bit / 2,
2547 bit % 2 ? "in":"out");
2548 ret += sprintf(str + ret, ", ");
2549 }
2550
2551 if (add) {
2552 ret += sprintf(str + ret, "Add:%s%s",
2553 (add & SLOT_FLAG) ? " slot":"",
2554 (add & EP0_FLAG) ? " ep0":"");
2555 add &= ~(SLOT_FLAG | EP0_FLAG);
2556 for_each_set_bit(bit, &add, 32)
2557 ret += sprintf(str + ret, " %d%s",
2558 bit / 2,
2559 bit % 2 ? "in":"out");
2560 }
2561 return str;
2562 }
2563
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2564 static inline const char *xhci_decode_slot_context(char *str,
2565 u32 info, u32 info2, u32 tt_info, u32 state)
2566 {
2567 u32 speed;
2568 u32 hub;
2569 u32 mtt;
2570 int ret = 0;
2571
2572 speed = info & DEV_SPEED;
2573 hub = info & DEV_HUB;
2574 mtt = info & DEV_MTT;
2575
2576 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2577 info & ROUTE_STRING_MASK,
2578 ({ char *s;
2579 switch (speed) {
2580 case SLOT_SPEED_FS:
2581 s = "full-speed";
2582 break;
2583 case SLOT_SPEED_LS:
2584 s = "low-speed";
2585 break;
2586 case SLOT_SPEED_HS:
2587 s = "high-speed";
2588 break;
2589 case SLOT_SPEED_SS:
2590 s = "super-speed";
2591 break;
2592 case SLOT_SPEED_SSP:
2593 s = "super-speed plus";
2594 break;
2595 default:
2596 s = "UNKNOWN speed";
2597 } s; }),
2598 mtt ? " multi-TT" : "",
2599 hub ? " Hub" : "",
2600 (info & LAST_CTX_MASK) >> 27,
2601 info2 & MAX_EXIT,
2602 DEVINFO_TO_ROOT_HUB_PORT(info2),
2603 DEVINFO_TO_MAX_PORTS(info2));
2604
2605 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2606 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2607 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2608 state & DEV_ADDR_MASK,
2609 xhci_slot_state_string(GET_SLOT_STATE(state)));
2610
2611 return str;
2612 }
2613
2614
xhci_portsc_link_state_string(u32 portsc)2615 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2616 {
2617 switch (portsc & PORT_PLS_MASK) {
2618 case XDEV_U0:
2619 return "U0";
2620 case XDEV_U1:
2621 return "U1";
2622 case XDEV_U2:
2623 return "U2";
2624 case XDEV_U3:
2625 return "U3";
2626 case XDEV_DISABLED:
2627 return "Disabled";
2628 case XDEV_RXDETECT:
2629 return "RxDetect";
2630 case XDEV_INACTIVE:
2631 return "Inactive";
2632 case XDEV_POLLING:
2633 return "Polling";
2634 case XDEV_RECOVERY:
2635 return "Recovery";
2636 case XDEV_HOT_RESET:
2637 return "Hot Reset";
2638 case XDEV_COMP_MODE:
2639 return "Compliance mode";
2640 case XDEV_TEST_MODE:
2641 return "Test mode";
2642 case XDEV_RESUME:
2643 return "Resume";
2644 default:
2645 break;
2646 }
2647 return "Unknown";
2648 }
2649
xhci_decode_portsc(char * str,u32 portsc)2650 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2651 {
2652 int ret;
2653
2654 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2655 portsc & PORT_POWER ? "Powered" : "Powered-off",
2656 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2657 portsc & PORT_PE ? "Enabled" : "Disabled",
2658 xhci_portsc_link_state_string(portsc),
2659 DEV_PORT_SPEED(portsc));
2660
2661 if (portsc & PORT_OC)
2662 ret += sprintf(str + ret, "OverCurrent ");
2663 if (portsc & PORT_RESET)
2664 ret += sprintf(str + ret, "In-Reset ");
2665
2666 ret += sprintf(str + ret, "Change: ");
2667 if (portsc & PORT_CSC)
2668 ret += sprintf(str + ret, "CSC ");
2669 if (portsc & PORT_PEC)
2670 ret += sprintf(str + ret, "PEC ");
2671 if (portsc & PORT_WRC)
2672 ret += sprintf(str + ret, "WRC ");
2673 if (portsc & PORT_OCC)
2674 ret += sprintf(str + ret, "OCC ");
2675 if (portsc & PORT_RC)
2676 ret += sprintf(str + ret, "PRC ");
2677 if (portsc & PORT_PLC)
2678 ret += sprintf(str + ret, "PLC ");
2679 if (portsc & PORT_CEC)
2680 ret += sprintf(str + ret, "CEC ");
2681 if (portsc & PORT_CAS)
2682 ret += sprintf(str + ret, "CAS ");
2683
2684 ret += sprintf(str + ret, "Wake: ");
2685 if (portsc & PORT_WKCONN_E)
2686 ret += sprintf(str + ret, "WCE ");
2687 if (portsc & PORT_WKDISC_E)
2688 ret += sprintf(str + ret, "WDE ");
2689 if (portsc & PORT_WKOC_E)
2690 ret += sprintf(str + ret, "WOE ");
2691
2692 return str;
2693 }
2694
xhci_decode_usbsts(char * str,u32 usbsts)2695 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2696 {
2697 int ret = 0;
2698
2699 ret = sprintf(str, " 0x%08x", usbsts);
2700
2701 if (usbsts == ~(u32)0)
2702 return str;
2703
2704 if (usbsts & STS_HALT)
2705 ret += sprintf(str + ret, " HCHalted");
2706 if (usbsts & STS_FATAL)
2707 ret += sprintf(str + ret, " HSE");
2708 if (usbsts & STS_EINT)
2709 ret += sprintf(str + ret, " EINT");
2710 if (usbsts & STS_PORT)
2711 ret += sprintf(str + ret, " PCD");
2712 if (usbsts & STS_SAVE)
2713 ret += sprintf(str + ret, " SSS");
2714 if (usbsts & STS_RESTORE)
2715 ret += sprintf(str + ret, " RSS");
2716 if (usbsts & STS_SRE)
2717 ret += sprintf(str + ret, " SRE");
2718 if (usbsts & STS_CNR)
2719 ret += sprintf(str + ret, " CNR");
2720 if (usbsts & STS_HCE)
2721 ret += sprintf(str + ret, " HCE");
2722
2723 return str;
2724 }
2725
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2726 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2727 {
2728 u8 ep;
2729 u16 stream;
2730 int ret;
2731
2732 ep = (doorbell & 0xff);
2733 stream = doorbell >> 16;
2734
2735 if (slot == 0) {
2736 sprintf(str, "Command Ring %d", doorbell);
2737 return str;
2738 }
2739 ret = sprintf(str, "Slot %d ", slot);
2740 if (ep > 0 && ep < 32)
2741 ret = sprintf(str + ret, "ep%d%s",
2742 ep / 2,
2743 ep % 2 ? "in" : "out");
2744 else if (ep == 0 || ep < 248)
2745 ret = sprintf(str + ret, "Reserved %d", ep);
2746 else
2747 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2748 if (stream)
2749 ret = sprintf(str + ret, " Stream %d", stream);
2750
2751 return str;
2752 }
2753
xhci_ep_state_string(u8 state)2754 static inline const char *xhci_ep_state_string(u8 state)
2755 {
2756 switch (state) {
2757 case EP_STATE_DISABLED:
2758 return "disabled";
2759 case EP_STATE_RUNNING:
2760 return "running";
2761 case EP_STATE_HALTED:
2762 return "halted";
2763 case EP_STATE_STOPPED:
2764 return "stopped";
2765 case EP_STATE_ERROR:
2766 return "error";
2767 default:
2768 return "INVALID";
2769 }
2770 }
2771
xhci_ep_type_string(u8 type)2772 static inline const char *xhci_ep_type_string(u8 type)
2773 {
2774 switch (type) {
2775 case ISOC_OUT_EP:
2776 return "Isoc OUT";
2777 case BULK_OUT_EP:
2778 return "Bulk OUT";
2779 case INT_OUT_EP:
2780 return "Int OUT";
2781 case CTRL_EP:
2782 return "Ctrl";
2783 case ISOC_IN_EP:
2784 return "Isoc IN";
2785 case BULK_IN_EP:
2786 return "Bulk IN";
2787 case INT_IN_EP:
2788 return "Int IN";
2789 default:
2790 return "INVALID";
2791 }
2792 }
2793
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2794 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2795 u32 info2, u64 deq, u32 tx_info)
2796 {
2797 int ret;
2798
2799 u32 esit;
2800 u16 maxp;
2801 u16 avg;
2802
2803 u8 max_pstr;
2804 u8 ep_state;
2805 u8 interval;
2806 u8 ep_type;
2807 u8 burst;
2808 u8 cerr;
2809 u8 mult;
2810
2811 bool lsa;
2812 bool hid;
2813
2814 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2815 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2816
2817 ep_state = info & EP_STATE_MASK;
2818 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2819 interval = CTX_TO_EP_INTERVAL(info);
2820 mult = CTX_TO_EP_MULT(info) + 1;
2821 lsa = !!(info & EP_HAS_LSA);
2822
2823 cerr = (info2 & (3 << 1)) >> 1;
2824 ep_type = CTX_TO_EP_TYPE(info2);
2825 hid = !!(info2 & (1 << 7));
2826 burst = CTX_TO_MAX_BURST(info2);
2827 maxp = MAX_PACKET_DECODED(info2);
2828
2829 avg = EP_AVG_TRB_LENGTH(tx_info);
2830
2831 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2832 xhci_ep_state_string(ep_state), mult,
2833 max_pstr, lsa ? "LSA " : "");
2834
2835 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2836 (1 << interval) * 125, esit, cerr);
2837
2838 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2839 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2840 burst, maxp, deq);
2841
2842 ret += sprintf(str + ret, "avg trb len %d", avg);
2843
2844 return str;
2845 }
2846
2847 #endif /* __LINUX_XHCI_HCD_H */
2848