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Searched refs:DPG_PIPE_ARBITRATION_CONTROL3 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.h79 SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\
133 uint32_t DPG_PIPE_ARBITRATION_CONTROL3; member
252 SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
Ddce_mem_input.c184 REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3, in dce60_program_urgency_watermark()
/drivers/gpu/drm/radeon/
Dsi.c2435 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2439 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2444 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2447 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2452 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
Dsid.h797 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 macro
/drivers/gpu/drm/amd/amdgpu/
Dsid.h800 #define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32 macro