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Searched refs:DSCC_PPS_CONFIG0 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.h41 SRI(DSCC_PPS_CONFIG0, DSCC, id),\
456 uint32_t DSCC_PPS_CONFIG0; member
Ddcn20_dsc.c581 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()