Searched refs:DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV (Results 1 – 2 of 2) sorted by relevance
188 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()195 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( in dsi_pll_28nm_clk_set_rate()276 DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; in dsi_pll_28nm_clk_recalc_rate()
1177 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV() function