Searched refs:DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK (Results 1 – 2 of 2) sorted by relevance
1184 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f macro1188 … ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET()
185 sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; in dsi_pll_28nm_clk_set_rate()