Home
last modified time | relevance | path

Searched refs:DSPSURF (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dfb_decoder.c247 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
Dhandlers.c755 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
2090 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2101 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2112 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
Dcmd_parser.c1281 info->surf_reg = DSPSURF(info->pipe); in gen8_decode_mi_display_flip()
1347 info->surf_reg = DSPSURF(info->pipe); in skl_decode_mi_display_flip()
/drivers/gpu/drm/i915/display/
Dintel_fbc.c207 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_recompress()
208 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_recompress()
Dintel_display.c4483 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_update_plane()
4516 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_disable_plane()
9353 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
9361 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
19052 DSPSURF(i)); in intel_display_capture_error_state()
/drivers/gpu/drm/i915/
Dintel_pm.c6882 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
6883 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
Di915_reg.h6534 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) macro