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Searched refs:DWB_OGAM_RAMA_END_CNTL1_R (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb.h96 SR(DWB_OGAM_RAMA_END_CNTL1_R),\
256 SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh),\
801 uint32_t DWB_OGAM_RAMA_END_CNTL1_R; member
Ddcn30_dwb_cm.c102 gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R); in dwb3_program_ogam_luta_settings()