/drivers/gpu/drm/msm/adreno/ |
D | adreno_common.xml.h | 110 ENDIAN_NONE = 0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/smu/ |
D | smu_8_0_enum.h | 518 ENDIAN_NONE = 0x0, enumerator
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D | smu_7_1_0_enum.h | 71 ENDIAN_NONE = 0x0, enumerator
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D | smu_7_1_3_enum.h | 75 ENDIAN_NONE = 0x0, enumerator
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D | smu_7_1_1_enum.h | 78 ENDIAN_NONE = 0x0, enumerator
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D | smu_7_1_2_enum.h | 78 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_enum.h | 518 ENDIAN_NONE = 0x0, enumerator
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D | bif_5_0_enum.h | 28 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
D | gmc_8_2_enum.h | 518 ENDIAN_NONE = 0x0, enumerator
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D | gmc_8_1_enum.h | 28 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_8_0_enum.h | 28 ENDIAN_NONE = 0x0, enumerator
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D | dce_10_0_enum.h | 603 ENDIAN_NONE = 0x0, enumerator
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D | dce_11_0_enum.h | 5090 ENDIAN_NONE = 0x0, enumerator
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D | dce_11_2_enum.h | 5102 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_6_0_enum.h | 531 ENDIAN_NONE = 0x0, enumerator
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D | uvd_5_0_enum.h | 41 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/oss/ |
D | oss_2_4_enum.h | 213 ENDIAN_NONE = 0x0, enumerator
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D | oss_3_0_enum.h | 327 ENDIAN_NONE = 0x0, enumerator
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D | oss_3_0_1_enum.h | 914 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/gca/ |
D | gfx_7_2_enum.h | 5154 ENDIAN_NONE = 0x0, enumerator
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D | gfx_8_1_enum.h | 6247 ENDIAN_NONE = 0x0, enumerator
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D | gfx_8_0_enum.h | 5688 ENDIAN_NONE = 0x0, enumerator
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/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v10_0.c | 1859 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v10_0_crtc_do_set_base()
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D | dce_v11_0.c | 1901 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v11_0_crtc_do_set_base()
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/drivers/gpu/drm/amd/include/ |
D | vega10_enum.h | 242 ENDIAN_NONE = 0x00000000, enumerator
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