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Searched refs:ENDIAN_NONE (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/msm/adreno/
Dadreno_common.xml.h110 ENDIAN_NONE = 0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h518 ENDIAN_NONE = 0x0, enumerator
Dsmu_7_1_0_enum.h71 ENDIAN_NONE = 0x0, enumerator
Dsmu_7_1_3_enum.h75 ENDIAN_NONE = 0x0, enumerator
Dsmu_7_1_1_enum.h78 ENDIAN_NONE = 0x0, enumerator
Dsmu_7_1_2_enum.h78 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h518 ENDIAN_NONE = 0x0, enumerator
Dbif_5_0_enum.h28 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h518 ENDIAN_NONE = 0x0, enumerator
Dgmc_8_1_enum.h28 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h28 ENDIAN_NONE = 0x0, enumerator
Ddce_10_0_enum.h603 ENDIAN_NONE = 0x0, enumerator
Ddce_11_0_enum.h5090 ENDIAN_NONE = 0x0, enumerator
Ddce_11_2_enum.h5102 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h531 ENDIAN_NONE = 0x0, enumerator
Duvd_5_0_enum.h41 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h213 ENDIAN_NONE = 0x0, enumerator
Doss_3_0_enum.h327 ENDIAN_NONE = 0x0, enumerator
Doss_3_0_1_enum.h914 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_enum.h5154 ENDIAN_NONE = 0x0, enumerator
Dgfx_8_1_enum.h6247 ENDIAN_NONE = 0x0, enumerator
Dgfx_8_0_enum.h5688 ENDIAN_NONE = 0x0, enumerator
/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c1859 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c1901 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v11_0_crtc_do_set_base()
/drivers/gpu/drm/amd/include/
Dvega10_enum.h242 ENDIAN_NONE = 0x00000000, enumerator

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