Searched refs:ETH_PLL_CTL0 (Results 1 – 1 of 1) sorted by relevance
19 #define ETH_PLL_CTL0 0x44 macro77 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()87 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()91 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()95 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()102 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()111 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()114 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()122 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_is_enabled()132 writel(0x29c0040a, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_init()[all …]