1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Samsung camera host interface (FIMC) registers definition
4 *
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
6 */
7
8 #ifndef FIMC_REG_H_
9 #define FIMC_REG_H_
10
11 #include <linux/bitops.h>
12
13 #include "fimc-core.h"
14
15 /* Input source format */
16 #define FIMC_REG_CISRCFMT 0x00
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
19 #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14)
20 #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14)
21 #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14)
22 #define FIMC_REG_CISRCFMT_ORDER422_CRYCBY (3 << 14)
23
24 /* Window offset */
25 #define FIMC_REG_CIWDOFST 0x04
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
29 #define FIMC_REG_CIWDOFST_HOROFF_MASK (0x7ff << 16)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
32 #define FIMC_REG_CIWDOFST_VEROFF_MASK (0xfff << 0)
33
34 /* Global control */
35 #define FIMC_REG_CIGCTRL 0x08
36 #define FIMC_REG_CIGCTRL_SWRST BIT(31)
37 #define FIMC_REG_CIGCTRL_CAMRST_A BIT(30)
38 #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29)
39 #define FIMC_REG_CIGCTRL_TESTPAT_NORMAL (0 << 27)
40 #define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
41 #define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
42 #define FIMC_REG_CIGCTRL_TESTPAT_VER_INC (3 << 27)
43 #define FIMC_REG_CIGCTRL_TESTPAT_MASK (3 << 27)
44 #define FIMC_REG_CIGCTRL_TESTPAT_SHIFT 27
45 #define FIMC_REG_CIGCTRL_INVPOLPCLK BIT(26)
46 #define FIMC_REG_CIGCTRL_INVPOLVSYNC BIT(25)
47 #define FIMC_REG_CIGCTRL_INVPOLHREF BIT(24)
48 #define FIMC_REG_CIGCTRL_IRQ_OVFEN BIT(22)
49 #define FIMC_REG_CIGCTRL_HREF_MASK BIT(21)
50 #define FIMC_REG_CIGCTRL_IRQ_LEVEL BIT(20)
51 #define FIMC_REG_CIGCTRL_IRQ_CLR BIT(19)
52 #define FIMC_REG_CIGCTRL_IRQ_ENABLE BIT(16)
53 #define FIMC_REG_CIGCTRL_SHDW_DISABLE BIT(12)
54 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
55 #define FIMC_REG_CIGCTRL_SELWB_A BIT(10)
56 #define FIMC_REG_CIGCTRL_CAM_JPEG BIT(8)
57 #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A BIT(7)
58 #define FIMC_REG_CIGCTRL_CAMIF_SELWB BIT(6)
59 /* 0 - ITU601; 1 - ITU709 */
60 #define FIMC_REG_CIGCTRL_CSC_ITU601_709 BIT(5)
61 #define FIMC_REG_CIGCTRL_INVPOLHSYNC BIT(4)
62 #define FIMC_REG_CIGCTRL_SELCAM_MIPI BIT(3)
63 #define FIMC_REG_CIGCTRL_INVPOLFIELD BIT(1)
64 #define FIMC_REG_CIGCTRL_INTERLACE BIT(0)
65
66 /* Window offset 2 */
67 #define FIMC_REG_CIWDOFST2 0x14
68 #define FIMC_REG_CIWDOFST2_HOROFF_MASK (0xfff << 16)
69 #define FIMC_REG_CIWDOFST2_VEROFF_MASK (0xfff << 0)
70
71 /* Output DMA Y/Cb/Cr plane start addresses */
72 #define FIMC_REG_CIOYSA(n) (0x18 + (n) * 4)
73 #define FIMC_REG_CIOCBSA(n) (0x28 + (n) * 4)
74 #define FIMC_REG_CIOCRSA(n) (0x38 + (n) * 4)
75
76 /* Target image format */
77 #define FIMC_REG_CITRGFMT 0x48
78 #define FIMC_REG_CITRGFMT_INROT90 BIT(31)
79 #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29)
80 #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29)
81 #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29)
82 #define FIMC_REG_CITRGFMT_RGB (3 << 29)
83 #define FIMC_REG_CITRGFMT_FMT_MASK (3 << 29)
84 #define FIMC_REG_CITRGFMT_HSIZE_MASK (0xfff << 16)
85 #define FIMC_REG_CITRGFMT_FLIP_SHIFT 14
86 #define FIMC_REG_CITRGFMT_FLIP_NORMAL (0 << 14)
87 #define FIMC_REG_CITRGFMT_FLIP_X_MIRROR (1 << 14)
88 #define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
89 #define FIMC_REG_CITRGFMT_FLIP_180 (3 << 14)
90 #define FIMC_REG_CITRGFMT_FLIP_MASK (3 << 14)
91 #define FIMC_REG_CITRGFMT_OUTROT90 BIT(13)
92 #define FIMC_REG_CITRGFMT_VSIZE_MASK (0xfff << 0)
93
94 /* Output DMA control */
95 #define FIMC_REG_CIOCTRL 0x4c
96 #define FIMC_REG_CIOCTRL_ORDER422_MASK (3 << 0)
97 #define FIMC_REG_CIOCTRL_ORDER422_YCBYCR (0 << 0)
98 #define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (1 << 0)
99 #define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (2 << 0)
100 #define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (3 << 0)
101 #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE BIT(2)
102 #define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3)
103 #define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3)
104 #define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
105 #define FIMC_REG_CIOCTRL_ALPHA_OUT_MASK (0xff << 4)
106 #define FIMC_REG_CIOCTRL_RGB16FMT_MASK (3 << 16)
107 #define FIMC_REG_CIOCTRL_RGB565 (0 << 16)
108 #define FIMC_REG_CIOCTRL_ARGB1555 (1 << 16)
109 #define FIMC_REG_CIOCTRL_ARGB4444 (2 << 16)
110 #define FIMC_REG_CIOCTRL_ORDER2P_SHIFT 24
111 #define FIMC_REG_CIOCTRL_ORDER2P_MASK (3 << 24)
112 #define FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
113
114 /* Pre-scaler control 1 */
115 #define FIMC_REG_CISCPRERATIO 0x50
116
117 #define FIMC_REG_CISCPREDST 0x54
118
119 /* Main scaler control */
120 #define FIMC_REG_CISCCTRL 0x58
121 #define FIMC_REG_CISCCTRL_SCALERBYPASS BIT(31)
122 #define FIMC_REG_CISCCTRL_SCALEUP_H BIT(30)
123 #define FIMC_REG_CISCCTRL_SCALEUP_V BIT(29)
124 #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE BIT(28)
125 #define FIMC_REG_CISCCTRL_CSCY2R_WIDE BIT(27)
126 #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO BIT(26)
127 #define FIMC_REG_CISCCTRL_INTERLACE BIT(25)
128 #define FIMC_REG_CISCCTRL_SCALERSTART BIT(15)
129 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
130 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
131 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
132 #define FIMC_REG_CISCCTRL_INRGB_FMT_MASK (3 << 13)
133 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
134 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
135 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
136 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
137 #define FIMC_REG_CISCCTRL_RGB_EXT BIT(10)
138 #define FIMC_REG_CISCCTRL_ONE2ONE BIT(9)
139 #define FIMC_REG_CISCCTRL_MHRATIO(x) ((x) << 16)
140 #define FIMC_REG_CISCCTRL_MVRATIO(x) ((x) << 0)
141 #define FIMC_REG_CISCCTRL_MHRATIO_MASK (0x1ff << 16)
142 #define FIMC_REG_CISCCTRL_MVRATIO_MASK (0x1ff << 0)
143 #define FIMC_REG_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16)
144 #define FIMC_REG_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0)
145
146 /* Target area */
147 #define FIMC_REG_CITAREA 0x5c
148 #define FIMC_REG_CITAREA_MASK 0x0fffffff
149
150 /* General status */
151 #define FIMC_REG_CISTATUS 0x64
152 #define FIMC_REG_CISTATUS_OVFIY BIT(31)
153 #define FIMC_REG_CISTATUS_OVFICB BIT(30)
154 #define FIMC_REG_CISTATUS_OVFICR BIT(29)
155 #define FIMC_REG_CISTATUS_VSYNC BIT(28)
156 #define FIMC_REG_CISTATUS_FRAMECNT_MASK (3 << 26)
157 #define FIMC_REG_CISTATUS_FRAMECNT_SHIFT 26
158 #define FIMC_REG_CISTATUS_WINOFF_EN BIT(25)
159 #define FIMC_REG_CISTATUS_IMGCPT_EN BIT(22)
160 #define FIMC_REG_CISTATUS_IMGCPT_SCEN BIT(21)
161 #define FIMC_REG_CISTATUS_VSYNC_A BIT(20)
162 #define FIMC_REG_CISTATUS_VSYNC_B BIT(19)
163 #define FIMC_REG_CISTATUS_OVRLB BIT(18)
164 #define FIMC_REG_CISTATUS_FRAME_END BIT(17)
165 #define FIMC_REG_CISTATUS_LASTCAPT_END BIT(16)
166 #define FIMC_REG_CISTATUS_VVALID_A BIT(15)
167 #define FIMC_REG_CISTATUS_VVALID_B BIT(14)
168
169 /* Indexes to the last and the currently processed buffer. */
170 #define FIMC_REG_CISTATUS2 0x68
171
172 /* Image capture control */
173 #define FIMC_REG_CIIMGCPT 0xc0
174 #define FIMC_REG_CIIMGCPT_IMGCPTEN BIT(31)
175 #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC BIT(30)
176 #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE BIT(25)
177 #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT BIT(18)
178
179 /* Frame capture sequence */
180 #define FIMC_REG_CICPTSEQ 0xc4
181
182 /* Image effect */
183 #define FIMC_REG_CIIMGEFF 0xd0
184 #define FIMC_REG_CIIMGEFF_IE_ENABLE BIT(30)
185 #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29)
186 #define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29)
187 #define FIMC_REG_CIIMGEFF_FIN_BYPASS (0 << 26)
188 #define FIMC_REG_CIIMGEFF_FIN_ARBITRARY (1 << 26)
189 #define FIMC_REG_CIIMGEFF_FIN_NEGATIVE (2 << 26)
190 #define FIMC_REG_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
191 #define FIMC_REG_CIIMGEFF_FIN_EMBOSSING (4 << 26)
192 #define FIMC_REG_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
193 #define FIMC_REG_CIIMGEFF_FIN_MASK (7 << 26)
194 #define FIMC_REG_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
195
196 /* Input DMA Y/Cb/Cr plane start address 0/1 */
197 #define FIMC_REG_CIIYSA(n) (0xd4 + (n) * 0x70)
198 #define FIMC_REG_CIICBSA(n) (0xd8 + (n) * 0x70)
199 #define FIMC_REG_CIICRSA(n) (0xdc + (n) * 0x70)
200
201 /* Real input DMA image size */
202 #define FIMC_REG_CIREAL_ISIZE 0xf8
203 #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN BIT(31)
204 #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS BIT(30)
205
206 /* Input DMA control */
207 #define FIMC_REG_MSCTRL 0xfc
208 #define FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK (0xf << 24)
209 #define FIMC_REG_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
210 #define FIMC_REG_MSCTRL_2P_IN_ORDER_SHIFT 16
211 #define FIMC_REG_MSCTRL_C_INT_IN_3PLANE (0 << 15)
212 #define FIMC_REG_MSCTRL_C_INT_IN_2PLANE (1 << 15)
213 #define FIMC_REG_MSCTRL_C_INT_IN_MASK (1 << 15)
214 #define FIMC_REG_MSCTRL_FLIP_SHIFT 13
215 #define FIMC_REG_MSCTRL_FLIP_MASK (3 << 13)
216 #define FIMC_REG_MSCTRL_FLIP_NORMAL (0 << 13)
217 #define FIMC_REG_MSCTRL_FLIP_X_MIRROR (1 << 13)
218 #define FIMC_REG_MSCTRL_FLIP_Y_MIRROR (2 << 13)
219 #define FIMC_REG_MSCTRL_FLIP_180 (3 << 13)
220 #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL BIT(12)
221 #define FIMC_REG_MSCTRL_ORDER422_SHIFT 4
222 #define FIMC_REG_MSCTRL_ORDER422_CRYCBY (0 << 4)
223 #define FIMC_REG_MSCTRL_ORDER422_YCRYCB (1 << 4)
224 #define FIMC_REG_MSCTRL_ORDER422_CBYCRY (2 << 4)
225 #define FIMC_REG_MSCTRL_ORDER422_YCBYCR (3 << 4)
226 #define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4)
227 #define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3)
228 #define FIMC_REG_MSCTRL_INPUT_MEMORY BIT(3)
229 #define FIMC_REG_MSCTRL_INPUT_MASK BIT(3)
230 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
231 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
232 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
233 #define FIMC_REG_MSCTRL_INFORMAT_RGB (3 << 1)
234 #define FIMC_REG_MSCTRL_INFORMAT_MASK (3 << 1)
235 #define FIMC_REG_MSCTRL_ENVID BIT(0)
236 #define FIMC_REG_MSCTRL_IN_BURST_COUNT(x) ((x) << 24)
237
238 /* Output DMA Y/Cb/Cr offset */
239 #define FIMC_REG_CIOYOFF 0x168
240 #define FIMC_REG_CIOCBOFF 0x16c
241 #define FIMC_REG_CIOCROFF 0x170
242
243 /* Input DMA Y/Cb/Cr offset */
244 #define FIMC_REG_CIIYOFF 0x174
245 #define FIMC_REG_CIICBOFF 0x178
246 #define FIMC_REG_CIICROFF 0x17c
247
248 /* Input DMA original image size */
249 #define FIMC_REG_ORGISIZE 0x180
250
251 /* Output DMA original image size */
252 #define FIMC_REG_ORGOSIZE 0x184
253
254 /* Real output DMA image size (extension register) */
255 #define FIMC_REG_CIEXTEN 0x188
256 #define FIMC_REG_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10)
257 #define FIMC_REG_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f)
258 #define FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10)
259 #define FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK 0x3f
260
261 #define FIMC_REG_CIDMAPARAM 0x18c
262 #define FIMC_REG_CIDMAPARAM_R_LINEAR (0 << 29)
263 #define FIMC_REG_CIDMAPARAM_R_64X32 (3 << 29)
264 #define FIMC_REG_CIDMAPARAM_W_LINEAR (0 << 13)
265 #define FIMC_REG_CIDMAPARAM_W_64X32 (3 << 13)
266 #define FIMC_REG_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
267
268 /* MIPI CSI image format */
269 #define FIMC_REG_CSIIMGFMT 0x194
270 #define FIMC_REG_CSIIMGFMT_YCBCR422_8BIT 0x1e
271 #define FIMC_REG_CSIIMGFMT_RAW8 0x2a
272 #define FIMC_REG_CSIIMGFMT_RAW10 0x2b
273 #define FIMC_REG_CSIIMGFMT_RAW12 0x2c
274 /* User defined formats. x = 0...16. */
275 #define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1)
276
277 /* Output frame buffer sequence mask */
278 #define FIMC_REG_CIFCNTSEQ 0x1fc
279
280 /* SYSREG ISP Writeback register address offsets */
281 #define SYSREG_ISPBLK 0x020c
282 #define SYSREG_ISPBLK_FIFORST_CAM_BLK BIT(7)
283
284 #define SYSREG_CAMBLK 0x0218
285 #define SYSREG_CAMBLK_FIFORST_ISP BIT(15)
286 #define SYSREG_CAMBLK_ISPWB_FULL_EN (7 << 20)
287
288 /*
289 * Function declarations
290 */
291 void fimc_hw_reset(struct fimc_dev *fimc);
292 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
293 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
294 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
295 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
296 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
297 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
298 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
299 void fimc_hw_enable_capture(struct fimc_ctx *ctx);
300 void fimc_hw_set_effect(struct fimc_ctx *ctx);
301 void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
302 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
303 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
304 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
305 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
306 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
307 int index);
308 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
309 struct fimc_source_info *cam);
310 void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
311 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
312 struct fimc_source_info *cam);
313 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
314 struct fimc_source_info *cam);
315 void fimc_hw_clear_irq(struct fimc_dev *dev);
316 void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on);
317 void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on);
318 void fimc_hw_disable_capture(struct fimc_dev *dev);
319 s32 fimc_hw_get_frame_index(struct fimc_dev *dev);
320 s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev);
321 int fimc_hw_camblk_cfg_writeback(struct fimc_dev *fimc);
322 void fimc_activate_capture(struct fimc_ctx *ctx);
323 void fimc_deactivate_capture(struct fimc_dev *fimc);
324
325 /**
326 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
327 * @mask: bitmask for the DMA output buffer registers, set to 0 to skip buffer
328 * This function masks output DMA ring buffers, it allows to select which of
329 * the 32 available output buffer address registers will be used by the DMA
330 * engine.
331 */
fimc_hw_set_dma_seq(struct fimc_dev * dev,u32 mask)332 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
333 {
334 writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ);
335 }
336
337 #endif /* FIMC_REG_H_ */
338