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Searched refs:FORMAT_CONTROL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp.c113 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
223 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c193 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp3_cnv_setup()
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp3_cnv_setup()
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp3_cnv_setup()
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp3_cnv_setup()
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp3_cnv_setup()
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp3_cnv_setup()
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp3_cnv_setup()
307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
Ddcn30_dpp.h134 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_ipp.h35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
168 uint32_t FORMAT_CONTROL; member
Ddcn10_dpp.c311 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
317 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
388 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
Ddcn10_dpp_cm.c714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
Ddcn10_dpp.h117 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1330 uint32_t FORMAT_CONTROL; \