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Searched refs:GDS_GWS_VMID0__SIZE__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c4126 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v7_0_ring_emit_gds_switch()
Dgfx_v8_0.c5217 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v8_0_ring_emit_gds_switch()
Dgfx_v9_0.c4217 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v9_0_ring_emit_gds_switch()
Dgfx_v10_0.c7231 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v10_0_ring_emit_gds_switch()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h15088 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
Dgfx_8_0_sh_mask.h17048 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
Dgfx_8_1_sh_mask.h17636 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h13659 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
Dgc_9_1_sh_mask.h14966 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
Dgc_9_2_1_sh_mask.h14824 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
Dgc_10_3_0_sh_mask.h19231 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
Dgc_10_1_0_sh_mask.h21084 #define GDS_GWS_VMID0__SIZE__SHIFT … macro