1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // SPDX-License-Identifier: GPL-2.0-or-later 3 /* 4 * (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 5 */ 6 7 #ifndef __SYSTEM_GLOBAL_H_INCLUDED__ 8 #define __SYSTEM_GLOBAL_H_INCLUDED__ 9 10 /* 11 * Create a list of HAS and IS properties that defines the system 12 * Those are common for both ISP2400 and ISP2401 13 * 14 * The configuration assumes the following 15 * - The system is hetereogeneous; Multiple cells and devices classes 16 * - The cell and device instances are homogeneous, each device type 17 * belongs to the same class 18 * - Device instances supporting a subset of the class capabilities are 19 * allowed 20 * 21 * We could manage different device classes through the enumerated 22 * lists (C) or the use of classes (C++), but that is presently not 23 * fully supported 24 * 25 * N.B. the 3 input formatters are of 2 different classess 26 */ 27 28 /* per-frame parameter handling support */ 29 #define SH_CSS_ENABLE_PER_FRAME_PARAMS 30 31 #define DMA_DDR_TO_VAMEM_WORKAROUND 32 #define DMA_DDR_TO_HMEM_WORKAROUND 33 34 /* 35 * The longest allowed (uninteruptible) bus transfer, does not 36 * take stalling into account 37 */ 38 #define HIVE_ISP_MAX_BURST_LENGTH 1024 39 40 /* 41 * Maximum allowed burst length in words for the ISP DMA 42 * This value is set to 2 to prevent the ISP DMA from blocking 43 * the bus for too long; as the input system can only buffer 44 * 2 lines on Moorefield and Cherrytrail, the input system buffers 45 * may overflow if blocked for too long (BZ 2726). 46 */ 47 #define ISP2400_DMA_MAX_BURST_LENGTH 128 48 #define ISP2401_DMA_MAX_BURST_LENGTH 2 49 50 #include <hive_isp_css_defs.h> 51 #include <type_support.h> 52 53 /* This interface is deprecated */ 54 #include "hive_types.h" 55 56 /* 57 * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply 58 */ 59 #define HRT_VADDRESS_WIDTH 32 60 61 #define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3) 62 #define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8) 63 64 /* The main bus connecting all devices */ 65 #define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH 66 #define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES 67 68 typedef u32 hrt_bus_align_t; 69 70 /* 71 * Enumerate the devices, device access through the API is by ID, 72 * through the DLI by address. The enumerator terminators are used 73 * to size the wiring arrays and as an exception value. 74 */ 75 typedef enum { 76 DDR0_ID = 0, 77 N_DDR_ID 78 } ddr_ID_t; 79 80 typedef enum { 81 ISP0_ID = 0, 82 N_ISP_ID 83 } isp_ID_t; 84 85 typedef enum { 86 SP0_ID = 0, 87 N_SP_ID 88 } sp_ID_t; 89 90 typedef enum { 91 MMU0_ID = 0, 92 MMU1_ID, 93 N_MMU_ID 94 } mmu_ID_t; 95 96 typedef enum { 97 DMA0_ID = 0, 98 N_DMA_ID 99 } dma_ID_t; 100 101 typedef enum { 102 GDC0_ID = 0, 103 GDC1_ID, 104 N_GDC_ID 105 } gdc_ID_t; 106 107 /* this extra define is needed because we want to use it also 108 in the preprocessor, and that doesn't work with enums. 109 */ 110 #define N_GDC_ID_CPP 2 111 112 typedef enum { 113 VAMEM0_ID = 0, 114 VAMEM1_ID, 115 VAMEM2_ID, 116 N_VAMEM_ID 117 } vamem_ID_t; 118 119 typedef enum { 120 BAMEM0_ID = 0, 121 N_BAMEM_ID 122 } bamem_ID_t; 123 124 typedef enum { 125 HMEM0_ID = 0, 126 N_HMEM_ID 127 } hmem_ID_t; 128 129 typedef enum { 130 IRQ0_ID = 0, /* GP IRQ block */ 131 IRQ1_ID, /* Input formatter */ 132 IRQ2_ID, /* input system */ 133 IRQ3_ID, /* input selector */ 134 N_IRQ_ID 135 } irq_ID_t; 136 137 typedef enum { 138 FIFO_MONITOR0_ID = 0, 139 N_FIFO_MONITOR_ID 140 } fifo_monitor_ID_t; 141 142 typedef enum { 143 GP_DEVICE0_ID = 0, 144 N_GP_DEVICE_ID 145 } gp_device_ID_t; 146 147 typedef enum { 148 GP_TIMER0_ID = 0, 149 GP_TIMER1_ID, 150 GP_TIMER2_ID, 151 GP_TIMER3_ID, 152 GP_TIMER4_ID, 153 GP_TIMER5_ID, 154 GP_TIMER6_ID, 155 GP_TIMER7_ID, 156 N_GP_TIMER_ID 157 } gp_timer_ID_t; 158 159 typedef enum { 160 GPIO0_ID = 0, 161 N_GPIO_ID 162 } gpio_ID_t; 163 164 typedef enum { 165 TIMED_CTRL0_ID = 0, 166 N_TIMED_CTRL_ID 167 } timed_ctrl_ID_t; 168 169 typedef enum { 170 INPUT_FORMATTER0_ID = 0, 171 INPUT_FORMATTER1_ID, 172 INPUT_FORMATTER2_ID, 173 INPUT_FORMATTER3_ID, 174 N_INPUT_FORMATTER_ID 175 } input_formatter_ID_t; 176 177 /* The IF RST is outside the IF */ 178 #define INPUT_FORMATTER0_SRST_OFFSET 0x0824 179 #define INPUT_FORMATTER1_SRST_OFFSET 0x0624 180 #define INPUT_FORMATTER2_SRST_OFFSET 0x0424 181 #define INPUT_FORMATTER3_SRST_OFFSET 0x0224 182 183 #define INPUT_FORMATTER0_SRST_MASK 0x0001 184 #define INPUT_FORMATTER1_SRST_MASK 0x0002 185 #define INPUT_FORMATTER2_SRST_MASK 0x0004 186 #define INPUT_FORMATTER3_SRST_MASK 0x0008 187 188 typedef enum { 189 INPUT_SYSTEM0_ID = 0, 190 N_INPUT_SYSTEM_ID 191 } input_system_ID_t; 192 193 typedef enum { 194 RX0_ID = 0, 195 N_RX_ID 196 } rx_ID_t; 197 198 enum mipi_port_id { 199 MIPI_PORT0_ID = 0, 200 MIPI_PORT1_ID, 201 MIPI_PORT2_ID, 202 N_MIPI_PORT_ID 203 }; 204 205 #define N_RX_CHANNEL_ID 4 206 207 /* Generic port enumeration with an internal port type ID */ 208 typedef enum { 209 CSI_PORT0_ID = 0, 210 CSI_PORT1_ID, 211 CSI_PORT2_ID, 212 TPG_PORT0_ID, 213 PRBS_PORT0_ID, 214 FIFO_PORT0_ID, 215 MEMORY_PORT0_ID, 216 N_INPUT_PORT_ID 217 } input_port_ID_t; 218 219 typedef enum { 220 CAPTURE_UNIT0_ID = 0, 221 CAPTURE_UNIT1_ID, 222 CAPTURE_UNIT2_ID, 223 ACQUISITION_UNIT0_ID, 224 DMA_UNIT0_ID, 225 CTRL_UNIT0_ID, 226 GPREGS_UNIT0_ID, 227 FIFO_UNIT0_ID, 228 IRQ_UNIT0_ID, 229 N_SUB_SYSTEM_ID 230 } sub_system_ID_t; 231 232 #define N_CAPTURE_UNIT_ID 3 233 #define N_ACQUISITION_UNIT_ID 1 234 #define N_CTRL_UNIT_ID 1 235 236 237 enum ia_css_isp_memories { 238 IA_CSS_ISP_PMEM0 = 0, 239 IA_CSS_ISP_DMEM0, 240 IA_CSS_ISP_VMEM0, 241 IA_CSS_ISP_VAMEM0, 242 IA_CSS_ISP_VAMEM1, 243 IA_CSS_ISP_VAMEM2, 244 IA_CSS_ISP_HMEM0, 245 IA_CSS_SP_DMEM0, 246 IA_CSS_DDR, 247 N_IA_CSS_MEMORIES 248 }; 249 250 #define IA_CSS_NUM_MEMORIES 9 251 /* For driver compatibility */ 252 #define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES 253 #define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES 254 255 /* 256 * ISP2401 specific enums 257 */ 258 259 typedef enum { 260 ISYS_IRQ0_ID = 0, /* port a */ 261 ISYS_IRQ1_ID, /* port b */ 262 ISYS_IRQ2_ID, /* port c */ 263 N_ISYS_IRQ_ID 264 } isys_irq_ID_t; 265 266 267 /* 268 * Input-buffer Controller. 269 */ 270 typedef enum { 271 IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */ 272 IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */ 273 IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ 274 N_IBUF_CTRL_ID 275 } ibuf_ctrl_ID_t; 276 /* end of Input-buffer Controller */ 277 278 /* 279 * Stream2MMIO. 280 */ 281 typedef enum { 282 STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */ 283 STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */ 284 STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */ 285 N_STREAM2MMIO_ID 286 } stream2mmio_ID_t; 287 288 typedef enum { 289 /* 290 * Stream2MMIO 0 has 8 SIDs that are indexed by 291 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. 292 * 293 * Stream2MMIO 1 has 4 SIDs that are indexed by 294 * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. 295 * 296 * Stream2MMIO 2 has 4 SIDs that are indexed by 297 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. 298 */ 299 STREAM2MMIO_SID0_ID = 0, 300 STREAM2MMIO_SID1_ID, 301 STREAM2MMIO_SID2_ID, 302 STREAM2MMIO_SID3_ID, 303 STREAM2MMIO_SID4_ID, 304 STREAM2MMIO_SID5_ID, 305 STREAM2MMIO_SID6_ID, 306 STREAM2MMIO_SID7_ID, 307 N_STREAM2MMIO_SID_ID 308 } stream2mmio_sid_ID_t; 309 /* end of Stream2MMIO */ 310 311 /** 312 * Input System 2401: CSI-MIPI recevier. 313 */ 314 typedef enum { 315 CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */ 316 CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */ 317 CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */ 318 N_CSI_RX_BACKEND_ID 319 } csi_rx_backend_ID_t; 320 321 typedef enum { 322 CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */ 323 CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */ 324 CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */ 325 #define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1) 326 } csi_rx_frontend_ID_t; 327 328 typedef enum { 329 CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */ 330 CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */ 331 CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */ 332 CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ 333 N_CSI_RX_DLANE_ID 334 } csi_rx_fe_dlane_ID_t; 335 /* end of CSI-MIPI receiver */ 336 337 typedef enum { 338 ISYS2401_DMA0_ID = 0, 339 N_ISYS2401_DMA_ID 340 } isys2401_dma_ID_t; 341 342 /** 343 * Pixel-generator. ("system_global.h") 344 */ 345 typedef enum { 346 PIXELGEN0_ID = 0, 347 PIXELGEN1_ID, 348 PIXELGEN2_ID, 349 N_PIXELGEN_ID 350 } pixelgen_ID_t; 351 /* end of pixel-generator. ("system_global.h") */ 352 353 typedef enum { 354 INPUT_SYSTEM_CSI_PORT0_ID = 0, 355 INPUT_SYSTEM_CSI_PORT1_ID, 356 INPUT_SYSTEM_CSI_PORT2_ID, 357 358 INPUT_SYSTEM_PIXELGEN_PORT0_ID, 359 INPUT_SYSTEM_PIXELGEN_PORT1_ID, 360 INPUT_SYSTEM_PIXELGEN_PORT2_ID, 361 362 N_INPUT_SYSTEM_INPUT_PORT_ID 363 } input_system_input_port_ID_t; 364 365 #define N_INPUT_SYSTEM_CSI_PORT 3 366 367 typedef enum { 368 ISYS2401_DMA_CHANNEL_0 = 0, 369 ISYS2401_DMA_CHANNEL_1, 370 ISYS2401_DMA_CHANNEL_2, 371 ISYS2401_DMA_CHANNEL_3, 372 ISYS2401_DMA_CHANNEL_4, 373 ISYS2401_DMA_CHANNEL_5, 374 ISYS2401_DMA_CHANNEL_6, 375 ISYS2401_DMA_CHANNEL_7, 376 ISYS2401_DMA_CHANNEL_8, 377 ISYS2401_DMA_CHANNEL_9, 378 ISYS2401_DMA_CHANNEL_10, 379 ISYS2401_DMA_CHANNEL_11, 380 N_ISYS2401_DMA_CHANNEL 381 } isys2401_dma_channel; 382 383 #endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ 384