Searched refs:HAL_SEQ_WCSS_UMAC_TCL_REG (Results 1 – 3 of 3) sorted by relevance
87 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()91 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()94 addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + in ath11k_hal_tx_set_dscp_tid_map()127 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()130 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()
1225 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()1226 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath11k_hal_srng_create_config()1231 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()1232 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath11k_hal_srng_create_config()1235 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()1236 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath11k_hal_srng_create_config()
43 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 macro