1 /******************************************************************************* 2 * 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenFabrics.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 *******************************************************************************/ 34 35 #ifndef I40IW_REGISTER_H 36 #define I40IW_REGISTER_H 37 38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 39 40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 41 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 42 #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) 43 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 44 #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT) 45 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 46 #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) 47 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 48 #define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) 49 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 50 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) 51 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 52 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK (0x3FF << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) 53 54 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 55 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 56 #define I40E_PFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 57 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 58 #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 59 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 60 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 61 62 #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ 63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 64 65 #define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15 66 #define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK (0x1 << I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) 67 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 68 #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 69 #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK (0x3 << I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) 70 #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */ 71 #define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 72 #define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK 0xFF 73 74 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */ 75 #define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0 76 #define I40E_PFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_PFPE_AEQALLOC_AECOUNT_SHIFT) 77 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */ 78 #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 79 #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 80 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */ 81 #define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0 82 #define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT) 83 #define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */ 84 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 85 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 86 #define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 87 #define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK (0x7 << I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 88 #define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 89 #define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK (0x3F << I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 90 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 91 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 92 #define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */ 93 #define I40E_PFPE_CQACK_PECQID_SHIFT 0 94 #define I40E_PFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_PFPE_CQACK_PECQID_SHIFT) 95 #define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */ 96 #define I40E_PFPE_CQARM_PECQID_SHIFT 0 97 #define I40E_PFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_PFPE_CQARM_PECQID_SHIFT) 98 #define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */ 99 #define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0 100 #define I40E_PFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_PFPE_CQPDB_WQHEAD_SHIFT) 101 #define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */ 102 #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 103 #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 104 #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 105 #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 106 #define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */ 107 #define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0 108 #define I40E_PFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_PFPE_CQPTAIL_WQTAIL_SHIFT) 109 #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 110 #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 111 #define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */ 112 #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 113 #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 114 #define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */ 115 #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 116 #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT) 117 #define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */ 118 #define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0 119 #define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT) 120 #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 121 #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 122 #define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */ 123 #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 124 #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 125 #define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */ 126 #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 127 #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 128 #define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */ 129 #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 130 #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 131 132 #define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */ 133 #define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0 134 #define I40E_PFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_PFPE_WQEALLOC_PEQPID_SHIFT) 135 #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 136 #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 137 138 #define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 139 #define I40E_VFPE_AEQALLOC_MAX_INDEX 127 140 #define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0 141 #define I40E_VFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC_AECOUNT_SHIFT) 142 #define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 143 #define I40E_VFPE_CCQPHIGH_MAX_INDEX 127 144 #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 145 #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 146 #define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 147 #define I40E_VFPE_CCQPLOW_MAX_INDEX 127 148 #define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0 149 #define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT) 150 #define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 151 #define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127 152 #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 153 #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 154 #define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 155 #define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK (0x7 << I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 156 #define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 157 #define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK (0x3F << I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 158 #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 159 #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 160 #define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 161 #define I40E_VFPE_CQACK_MAX_INDEX 127 162 #define I40E_VFPE_CQACK_PECQID_SHIFT 0 163 #define I40E_VFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK_PECQID_SHIFT) 164 #define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 165 #define I40E_VFPE_CQARM_MAX_INDEX 127 166 #define I40E_VFPE_CQARM_PECQID_SHIFT 0 167 #define I40E_VFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM_PECQID_SHIFT) 168 #define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 169 #define I40E_VFPE_CQPDB_MAX_INDEX 127 170 #define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0 171 #define I40E_VFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB_WQHEAD_SHIFT) 172 #define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 173 #define I40E_VFPE_CQPERRCODES_MAX_INDEX 127 174 #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 175 #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 176 #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 177 #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 178 #define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 179 #define I40E_VFPE_CQPTAIL_MAX_INDEX 127 180 #define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0 181 #define I40E_VFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL_WQTAIL_SHIFT) 182 #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 183 #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 184 #define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 185 #define I40E_VFPE_IPCONFIG0_MAX_INDEX 127 186 #define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0 187 #define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT) 188 #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 189 #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 190 #define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 191 #define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127 192 #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 193 #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 194 #define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 195 #define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127 196 #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 197 #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 198 #define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 199 #define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127 200 #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 201 #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 202 #define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 203 #define I40E_VFPE_WQEALLOC_MAX_INDEX 127 204 #define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0 205 #define I40E_VFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC_PEQPID_SHIFT) 206 #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 207 #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 208 209 #define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */ 210 #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0 211 #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT) 212 #define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */ 213 #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0 214 #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT) 215 #define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */ 216 #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0 217 #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT) 218 #define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */ 219 #define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0 220 #define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK (0xFFFF << I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT) 221 #define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17 222 #define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK (0x1 << I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT) 223 #define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18 224 #define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK (0x1 << I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT) 225 #define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */ 226 #define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0 227 #define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK (0x1 << I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT) 228 #define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 229 #define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15 230 #define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 231 #define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK (0xFFFF << I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 232 #define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 233 #define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15 234 #define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 235 #define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK (0xFFFF << I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 236 #define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 237 #define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15 238 #define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0 239 #define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK (0xFFFF << I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT) 240 #define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */ 241 #define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0 242 #define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK (0xFF << I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT) 243 #define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */ 244 #define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0 245 #define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK (0xFF << I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT) 246 #define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */ 247 #define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0 248 #define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK (0xFF << I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT) 249 #define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26 250 #define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK (0x1 << I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT) 251 #define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27 252 #define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK (0x1 << I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT) 253 #define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28 254 #define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK (0x1 << I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT) 255 #define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29 256 #define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK (0x1 << I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT) 257 #define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30 258 #define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK (0x1 << I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT) 259 #define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31 260 #define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK (0x1 << I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT) 261 #define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */ 262 #define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0 263 #define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK (0xFF << I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT) 264 #define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */ 265 #define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0 266 #define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK (0xFF << I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT) 267 #define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */ 268 #define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0 269 #define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK (0x1 << I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT) 270 #define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 271 #define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31 272 #define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 273 #define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK (0xFFFF << I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 274 #define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 275 #define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31 276 #define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 277 #define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK (0xFFFF << I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 278 #define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 279 #define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31 280 #define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0 281 #define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK (0xFFFF << I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT) 282 #define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 283 #define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31 284 #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0 285 #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT) 286 #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8 287 #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT) 288 #define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 289 #define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31 290 #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 291 #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 292 #define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 293 #define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31 294 #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 295 #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT) 296 #define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 297 #define I40E_GLPE_VFUDACTRL_MAX_INDEX 31 298 #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0 299 #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT) 300 #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1 301 #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT) 302 #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2 303 #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT) 304 #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3 305 #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT) 306 #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 307 #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT) 308 #define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 309 #define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31 310 #define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0 311 #define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT) 312 #define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31 313 #define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK (0x1 << I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT) 314 315 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 316 #define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15 317 #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 318 #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 319 #define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 320 #define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15 321 #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 322 #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 323 #define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 324 #define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15 325 #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 326 #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 327 #define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 328 #define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15 329 #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 330 #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 331 #define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 332 #define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15 333 #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 334 #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 335 #define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 336 #define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15 337 #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 338 #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 339 #define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 340 #define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15 341 #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 342 #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 343 #define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 344 #define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15 345 #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 346 #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 347 #define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 348 #define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15 349 #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 350 #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 351 #define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 352 #define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15 353 #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 354 #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 355 #define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 356 #define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15 357 #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 358 #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 359 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 360 #define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15 361 #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 362 #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 363 #define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 364 #define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15 365 #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 366 #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 367 #define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 368 #define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15 369 #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 370 #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 371 #define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 372 #define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15 373 #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 374 #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 375 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 376 #define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15 377 #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 378 #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 379 #define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 380 #define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15 381 #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 382 #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 383 #define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 384 #define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15 385 #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 386 #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 387 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 388 #define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15 389 #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 390 #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 391 #define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 392 #define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15 393 #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 394 #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 395 #define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 396 #define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15 397 #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 398 #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 399 #define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 400 #define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15 401 #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 402 #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 403 #define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 404 #define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15 405 #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 406 #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 407 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 408 #define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15 409 #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 410 #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 411 #define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 412 #define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15 413 #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 414 #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 415 #define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 416 #define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15 417 #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 418 #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 419 #define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 420 #define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15 421 #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 422 #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 423 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 424 #define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15 425 #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 426 #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 427 #define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 428 #define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15 429 #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 430 #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 431 #define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 432 #define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15 433 #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 434 #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 435 #define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 436 #define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15 437 #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 438 #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 439 #define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 440 #define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15 441 #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 442 #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 443 #define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 444 #define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15 445 #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 446 #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 447 #define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 448 #define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15 449 #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 450 #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 451 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 452 #define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15 453 #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 454 #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 455 #define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 456 #define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15 457 #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 458 #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 459 #define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 460 #define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15 461 #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 462 #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 463 #define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 464 #define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15 465 #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 466 #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 467 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 468 #define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15 469 #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 470 #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 471 #define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 472 #define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15 473 #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 474 #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 475 #define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 476 #define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15 477 #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 478 #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 479 #define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 480 #define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15 481 #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 482 #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 483 #define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 484 #define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15 485 #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 486 #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 487 #define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 488 #define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15 489 #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 490 #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 491 #define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 492 #define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15 493 #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 494 #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 495 #define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 496 #define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15 497 #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 498 #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 499 #define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 500 #define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15 501 #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 502 #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 503 #define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 504 #define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15 505 #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 506 #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 507 #define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 508 #define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15 509 #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 510 #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 511 #define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 512 #define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15 513 #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 514 #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 515 #define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 516 #define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15 517 #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 518 #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 519 #define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 520 #define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15 521 #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 522 #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 523 #define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 524 #define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15 525 #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 526 #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 527 #define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 528 #define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15 529 #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 530 #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 531 #define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 532 #define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15 533 #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 534 #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 535 #define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 536 #define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15 537 #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 538 #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 539 #define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 540 #define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15 541 #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 542 #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 543 #define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 544 #define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15 545 #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 546 #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 547 #define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 548 #define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15 549 #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 550 #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 551 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 552 #define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15 553 #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 554 #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 555 #define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 556 #define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15 557 #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0 558 #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT) 559 #define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 560 #define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15 561 #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0 562 #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT) 563 #define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 564 #define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15 565 #define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0 566 #define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT) 567 #define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 568 #define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15 569 #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0 570 #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT) 571 #define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 572 #define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15 573 #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 574 #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 575 #define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 576 #define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15 577 #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 578 #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 579 #define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 580 #define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15 581 #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 582 #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 583 #define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 584 #define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15 585 #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 586 #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 587 #define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 588 #define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15 589 #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 590 #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 591 #define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 592 #define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15 593 #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 594 #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 595 #define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 596 #define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15 597 #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 598 #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 599 #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 600 #define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15 601 #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 602 #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 603 #define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 604 #define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15 605 #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 606 #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 607 #define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 608 #define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15 609 #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 610 #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 611 #define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */ 612 #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0 613 #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT) 614 #define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */ 615 #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0 616 #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT) 617 #define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */ 618 #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0 619 #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT) 620 #define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */ 621 #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0 622 #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT) 623 #define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */ 624 #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0 625 #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT) 626 #define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */ 627 #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0 628 #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT) 629 #define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */ 630 #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0 631 #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT) 632 #define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */ 633 #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0 634 #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT) 635 #define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */ 636 #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0 637 #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT) 638 #define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */ 639 #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0 640 #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT) 641 #define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */ 642 #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0 643 #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT) 644 #define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */ 645 #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0 646 #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT) 647 #define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */ 648 #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0 649 #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT) 650 #define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */ 651 #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0 652 #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT) 653 #define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */ 654 #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0 655 #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT) 656 #define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */ 657 #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0 658 #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT) 659 #define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */ 660 #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0 661 #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT) 662 #define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */ 663 #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0 664 #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT) 665 #define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */ 666 #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0 667 #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT) 668 #define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */ 669 #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0 670 #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT) 671 #define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */ 672 #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0 673 #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT) 674 #define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */ 675 #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0 676 #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT) 677 #define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 678 #define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31 679 #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 680 #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 681 #define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 682 #define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31 683 #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 684 #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 685 #define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 686 #define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31 687 #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 688 #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 689 #define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 690 #define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31 691 #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 692 #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 693 #define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 694 #define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31 695 #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 696 #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 697 #define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 698 #define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31 699 #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 700 #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 701 #define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 702 #define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31 703 #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 704 #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 705 #define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 706 #define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31 707 #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 708 #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 709 #define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 710 #define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31 711 #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 712 #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 713 #define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 714 #define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31 715 #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 716 #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 717 #define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 718 #define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31 719 #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 720 #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 721 #define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 722 #define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31 723 #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 724 #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 725 #define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 726 #define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31 727 #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 728 #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 729 #define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 730 #define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31 731 #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 732 #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 733 #define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 734 #define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31 735 #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 736 #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 737 #define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 738 #define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31 739 #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 740 #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 741 #define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 742 #define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31 743 #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 744 #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 745 #define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 746 #define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31 747 #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 748 #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 749 #define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 750 #define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31 751 #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 752 #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 753 #define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 754 #define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31 755 #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 756 #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 757 #define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 758 #define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31 759 #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 760 #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 761 #define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 762 #define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31 763 #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 764 #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 765 #define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 766 #define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31 767 #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 768 #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 769 #define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 770 #define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31 771 #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 772 #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 773 #define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 774 #define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31 775 #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 776 #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 777 #define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 778 #define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31 779 #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 780 #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 781 #define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 782 #define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31 783 #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 784 #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 785 #define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 786 #define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31 787 #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 788 #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 789 #define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 790 #define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31 791 #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 792 #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 793 #define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 794 #define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31 795 #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 796 #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 797 #define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 798 #define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31 799 #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 800 #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 801 #define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 802 #define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31 803 #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 804 #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 805 #define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 806 #define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31 807 #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 808 #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 809 #define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 810 #define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31 811 #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 812 #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 813 #define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 814 #define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31 815 #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 816 #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 817 #define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 818 #define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31 819 #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 820 #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 821 #define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 822 #define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31 823 #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 824 #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 825 #define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 826 #define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31 827 #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 828 #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 829 #define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 830 #define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31 831 #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 832 #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 833 #define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 834 #define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31 835 #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 836 #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 837 #define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 838 #define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31 839 #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 840 #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 841 #define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 842 #define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31 843 #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 844 #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 845 #define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 846 #define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31 847 #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 848 #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 849 #define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 850 #define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31 851 #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 852 #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 853 #define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 854 #define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31 855 #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 856 #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 857 #define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 858 #define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31 859 #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 860 #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 861 #define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 862 #define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31 863 #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 864 #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 865 #define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 866 #define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31 867 #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 868 #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 869 #define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 870 #define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31 871 #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 872 #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 873 #define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 874 #define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31 875 #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 876 #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 877 #define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 878 #define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31 879 #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 880 #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 881 #define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 882 #define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31 883 #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 884 #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 885 #define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 886 #define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31 887 #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 888 #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 889 #define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 890 #define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31 891 #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 892 #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 893 #define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 894 #define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31 895 #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 896 #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 897 #define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 898 #define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31 899 #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 900 #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 901 #define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 902 #define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31 903 #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 904 #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 905 #define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 906 #define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31 907 #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 908 #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 909 #define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 910 #define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31 911 #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 912 #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 913 #define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 914 #define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31 915 #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 916 #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 917 #define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 918 #define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31 919 #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0 920 #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT) 921 #define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 922 #define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31 923 #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0 924 #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT) 925 #define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 926 #define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31 927 #define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0 928 #define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT) 929 #define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 930 #define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31 931 #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0 932 #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT) 933 #define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 934 #define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31 935 #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 936 #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 937 #define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 938 #define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31 939 #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 940 #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 941 #define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 942 #define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31 943 #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 944 #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 945 #define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 946 #define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31 947 #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 948 #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 949 #define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 950 #define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31 951 #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 952 #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 953 #define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 954 #define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31 955 #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 956 #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 957 #define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 958 #define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31 959 #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 960 #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 961 #define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 962 #define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31 963 #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 964 #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 965 #define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 966 #define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31 967 #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 968 #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 969 #define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 970 #define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31 971 #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 972 #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 973 974 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ 975 #define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 976 #define I40E_VFPE_AEQALLOC1_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) 977 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ 978 #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 979 #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) 980 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ 981 #define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 982 #define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) 983 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ 984 #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 985 #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) 986 #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 987 #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK (0x7 << I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) 988 #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 989 #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK (0x3F << I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) 990 #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 991 #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) 992 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ 993 #define I40E_VFPE_CQACK1_PECQID_SHIFT 0 994 #define I40E_VFPE_CQACK1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK1_PECQID_SHIFT) 995 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ 996 #define I40E_VFPE_CQARM1_PECQID_SHIFT 0 997 #define I40E_VFPE_CQARM1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM1_PECQID_SHIFT) 998 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ 999 #define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 1000 #define I40E_VFPE_CQPDB1_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB1_WQHEAD_SHIFT) 1001 #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ 1002 #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 1003 #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) 1004 #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 1005 #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) 1006 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ 1007 #define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 1008 #define I40E_VFPE_CQPTAIL1_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) 1009 #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 1010 #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) 1011 #define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ 1012 #define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 1013 #define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) 1014 #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 1015 #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) 1016 #define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ 1017 #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 1018 #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) 1019 #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ 1020 #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 1021 #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) 1022 #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ 1023 #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 1024 #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) 1025 #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ 1026 #define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 1027 #define I40E_VFPE_WQEALLOC1_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) 1028 #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 1029 #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) 1030 #endif /* I40IW_REGISTER_H */ 1031