Searched refs:IRQ_REG_ENTRY (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| D | irq_service_dce120.c | 105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
121 IRQ_REG_ENTRY(HPD, reg_num,\
130 IRQ_REG_ENTRY(HPD, reg_num,\
138 IRQ_REG_ENTRY(DCP, reg_num, \
147 IRQ_REG_ENTRY(CRTC, reg_num,\
155 IRQ_REG_ENTRY(CRTC, reg_num,\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| D | irq_service_dcn21.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
207 IRQ_REG_ENTRY(HPD, reg_num,\
216 IRQ_REG_ENTRY(HPD, reg_num,\
224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
235 IRQ_REG_ENTRY(OTG, reg_num,\
243 IRQ_REG_ENTRY(OTG, reg_num,\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| D | irq_service_dcn30.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
213 IRQ_REG_ENTRY(HPD, reg_num,\
222 IRQ_REG_ENTRY(HPD, reg_num,\
230 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
241 IRQ_REG_ENTRY(OTG, reg_num,\
249 IRQ_REG_ENTRY(OTG, reg_num,\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| D | irq_service_dcn10.c | 186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
202 IRQ_REG_ENTRY(HPD, reg_num,\
211 IRQ_REG_ENTRY(HPD, reg_num,\
219 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
230 IRQ_REG_ENTRY(OTG, reg_num,\
238 IRQ_REG_ENTRY(OTG, reg_num,\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| D | irq_service_dcn20.c | 188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
206 IRQ_REG_ENTRY(HPD, reg_num,\
215 IRQ_REG_ENTRY(HPD, reg_num,\
223 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
234 IRQ_REG_ENTRY(OTG, reg_num,\
242 IRQ_REG_ENTRY(OTG, reg_num,\
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