Searched refs:LB_MEMORY_CTRL (Results 1 – 9 of 9) sorted by relevance
/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_transform.h | 93 SRI(LB_MEMORY_CTRL, LB, id), \ 247 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ 248 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ 602 uint32_t LB_MEMORY_CTRL; member
|
D | dce_transform.c | 418 REG_SET_2(LB_MEMORY_CTRL, 0, in dce_transform_set_scaler()
|
/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_dpp_dscl.c | 228 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
|
D | dcn10_dpp.h | 58 SRI(LB_MEMORY_CTRL, DSCL, id), \ 1101 uint32_t LB_MEMORY_CTRL; \
|
/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_dpp.h | 103 SRI(LB_MEMORY_CTRL, DSCL, id), \
|
/drivers/gpu/drm/radeon/ |
D | cikd.h | 864 #define LB_MEMORY_CTRL 0x6b04 macro
|
D | cik.c | 8851 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
|
/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v10_0.c | 629 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v10_0_line_buffer_adjust()
|
D | dce_v11_0.c | 655 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v11_0_line_buffer_adjust()
|