Home
last modified time | relevance | path

Searched refs:LVDS (Results 1 – 25 of 43) sorted by relevance

12

/drivers/gpu/drm/bridge/
DKconfig66 tristate "Transparent LVDS encoders and decoders support"
71 Support for transparent LVDS encoders and decoders that don't
81 GE B850v3 that convert dual channel LVDS
102 tristate "NXP PTN3460 DP/LVDS bridge"
107 NXP PTN3460 eDP-LVDS bridge chip driver.
110 tristate "Parade eDP/LVDS bridge"
116 Parade eDP-LVDS bridge chip driver.
166 tristate "Thine THC63LVD1024 LVDS decoder bridge"
169 Thine THC63LVD1024 LVDS/parallel converter driver.
180 tristate "TC358764 DSI/LVDS bridge"
[all …]
/drivers/gpu/drm/rockchip/
DKconfig64 bool "Rockchip LVDS support"
68 Choose this option to enable support for Rockchip LVDS controllers.
69 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
70 support LVDS, rgb, dual LVDS output mode. say Y to enable its
/drivers/gpu/drm/imx/
DKconfig29 tristate "Support for LVDS displays"
33 Choose this to enable the internal LVDS Display Bridge (LDB)
/drivers/gpu/drm/rcar-du/
DKconfig34 bool "R-Car DU LVDS Encoder Support"
38 Enable support for the R-Car Display Unit embedded LVDS encoders.
Drcar_du_of_lvds_r8a7791.dts3 * rcar_du_of_lvds_r8a7791.dts - Legacy LVDS DT bindings conversion for R8A7791
Drcar_du_of_lvds_r8a7793.dts3 * rcar_du_of_lvds_r8a7793.dts - Legacy LVDS DT bindings conversion for R8A7793
Drcar_du_of_lvds_r8a7795.dts3 * rcar_du_of_lvds_r8a7795.dts - Legacy LVDS DT bindings conversion for R8A7795
Drcar_du_of_lvds_r8a7796.dts3 * rcar_du_of_lvds_r8a7796.dts - Legacy LVDS DT bindings conversion for R8A7796
Drcar_du_of_lvds_r8a7790.dts3 * rcar_du_of_lvds_r8a7790.dts - Legacy LVDS DT bindings conversion for R8A7790
/drivers/phy/rockchip/
DKconfig51 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
56 Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
/drivers/gpu/drm/gma500/
Dpsb_intel_display.c224 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
244 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
245 REG_READ(LVDS); in psb_intel_crtc_mode_set()
316 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in psb_intel_crtc_clock_get()
Dcdv_intel_display.c707 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
738 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set()
757 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
758 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
857 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
DKconfig21 platforms with LVDS ports. MIPI is not currently supported.
Dpsb_intel_lvds.c265 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
318 REG_WRITE(LVDS, lvds_priv->saveLVDS); in psb_intel_lvds_restore()
760 lvds = REG_READ(LVDS); in psb_intel_lvds_init()
Doaktrail_lvds.c102 lvds_port = (REG_READ(LVDS) & in oaktrail_lvds_mode_set()
112 REG_WRITE(LVDS, lvds_port); in oaktrail_lvds_mode_set()
Doaktrail_device.c238 regs->psb.saveLVDS = PSB_RVDC32(LVDS); in oaktrail_save_display_registers()
362 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/ in oaktrail_restore_display_registers()
Dcdv_device.c282 regs->cdv.saveLVDS = REG_READ(LVDS); in cdv_save_display_registers()
350 REG_WRITE(LVDS, regs->cdv.saveLVDS); in cdv_restore_display_registers()
/drivers/video/fbdev/nvidia/
Dnv_setup.c637 par->LVDS = 0; in NVCommonSetup()
641 par->LVDS = 1; in NVCommonSetup()
642 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); in NVCommonSetup()
Dnv_type.h135 int LVDS; member
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dsornv50.c75 case 0: state->proto = LVDS; state->link = 1; break; in nv50_sor_state()
Dsorgv100.c66 case 0: state->proto = LVDS; state->link = 1; break; in gv100_sor_state()
Dior.h29 LVDS, enumerator
Dsorgf119.c144 case 0: state->proto = LVDS; state->link = 1; break; in gf119_sor_state()
/drivers/gpu/drm/radeon/
Dsmu7.h161 LVDS, enumerator
/drivers/gpu/drm/amd/pm/inc/
Dsmu7.h180 LVDS, enumerator

12