| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllnv04.c | 151 int M1, N1, M2, N2, log2P; in getMNP_double() local
177 for (M2 = minM2; M2 <= maxM2; M2++) { in getMNP_double()
178 if (calcclk1/M2 < minU2) in getMNP_double()
180 if (calcclk1/M2 > maxU2) in getMNP_double()
184 N2 = (clkP * M2 + calcclk1/2) / calcclk1; in getMNP_double()
192 if (N2/M2 < 4 || N2/M2 > 10) in getMNP_double()
195 calcclk2 = calcclk1 * N2 / M2; in getMNP_double()
214 *pM2 = M2; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
236 *M2 = 1; in nv04_pll_calc()
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| D | nv40.c | 62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2() local
71 if (M2) in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
160 if (N2 == M2) { in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
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| D | nv04.c | 35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
42 pv->M2 = M2; in nv04_clk_pll_calc()
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| D | nv50.c | 166 int N1, N2, M1, M2; in read_pll() local
175 M2 = (coef & 0x00ff0000) >> 16; in read_pll()
181 if (M2) in read_pll()
182 freq = freq * N2 / M2; in read_pll()
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| D | pll.h | 9 int *N1, int *M1, int *N2, int *M2, int *P);
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ in setPLL_double_highregs()
217 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; in setPLL_double_highregs()
296 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; in setPLL_double_lowregs()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
378 pv.M2 = M2; in nv04_devinit_pll_set()
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| D | nv50.c | 41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
62 (M2 << 16) | N2); in nv50_devinit_pll_set()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
55 if (N2 == M2) { in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
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| D | ramgk104.c | 134 int N2, M2, P2; member
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
990 int *N2, int *M2, int *P2) in gk104_pll_calc_hiclk() argument
997 *M2 = 1; in gk104_pll_calc_hiclk()
1067 &ram->N2, &ram->M2, &ram->P2); in gk104_ram_calc_xits()
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| D | ramnv50.c | 231 int N1, M1, N2, M2, P; in nv50_ram_calc() local
332 &N1, &M1, &N2, &M2, &P); in nv50_ram_calc()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | pll.h | 9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
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| /drivers/soc/renesas/ |
| D | Kconfig | 85 bool "ARM32 Platform support for R-Car M2-N"
92 bool "ARM32 Platform support for R-Car M2-W"
315 bool "System Controller support for R-Car M2-W/N" if COMPILE_TEST
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
208 if (!pv->M1 || !pv->M2) in nouveau_hw_pllvals_to_clk()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
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| D | crtc.c | 166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
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| /drivers/pinctrl/renesas/ |
| D | Kconfig | 114 bool "pin control support for R-Car M2-N" if COMPILE_TEST
118 bool "pin control support for R-Car M2-W" if COMPILE_TEST
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| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 1513 #define M2 184 macro
1514 SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
1515 SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8);
1516 PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8));
1517 FUNC_GROUP_DECL(ADC8, M2);
2060 ASPEED_PINCTRL_PIN(M2),
2508 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
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| /drivers/clk/renesas/ |
| D | Kconfig | 106 bool "R-Car M2-W/N clock support" if COMPILE_TEST
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| /drivers/bus/mhi/host/ |
| D | debugfs.c | 28 seq_printf(m, "M0: %u M2: %u M3: %u", mhi_cntrl->M0, mhi_cntrl->M2, in mhi_debugfs_states_show()
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| D | pm.c | 332 mhi_cntrl->M2++; in mhi_pm_m1_transition()
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| /drivers/hwmon/ |
| D | Kconfig | 694 the x3350, x3550, x3650, x3655, x3755, x3850 M2, x3950 M2,
|