| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk20a.h | 30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
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| D | gm20b.c | 41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
57 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_pllg_read_mnp()
201 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH)); in gm20b_dvfs_calc_det_coeff()
254 rem = ((u32)n) & MASK(DFS_DET_RANGE); in gm20b_dvfs_calc_ndiv()
259 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_dvfs_calc_ndiv()
536 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1), in gm20b_dvfs_program_ext_cal()
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); in gm20b_clk_init_dvfs()
[all …]
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| D | gk20a.c | 71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
82 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; in gk20a_pllg_write_mnp()
83 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; in gk20a_pllg_write_mnp()
84 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; in gk20a_pllg_write_mnp()
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| /drivers/gpu/drm/amd/display/dc/gpio/ |
| D | hw_gpio.c | 45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
164 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
172 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
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| D | ddc_regs.h | 41 DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
64 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
81 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
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| D | generic_regs.h | 38 GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
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| D | hpd_regs.h | 46 HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
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| /drivers/scsi/sym53c8xx_2/ |
| D | sym_fw2.h | 228 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
316 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
348 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
438 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
462 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
521 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
681 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
898 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
904 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1073 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| D | sym_fw1.h | 236 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
363 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
453 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
478 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
538 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
704 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
949 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
955 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1187 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1207 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_ade_reg.h | 13 #define MASK(x) (BIT(x) - 1) macro
17 #define FRM_END_START_MASK MASK(2)
50 #define CH_OVLY_SEL_MASK MASK(2)
99 #define QOSGENERATOR_MODE_MASK MASK(2)
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| D | kirin_drm_ade.c | 102 MASK(1), !!val); in ade_update_reload_bit()
128 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); in ade_init()
129 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); in ade_init()
130 writel(MASK(32), base + ADE_RELOAD_DIS(0)); in ade_init()
131 writel(MASK(32), base + ADE_RELOAD_DIS(1)); in ade_init()
285 MASK(1), 1); in ade_crtc_enable_vblank()
302 MASK(1), 0); in ade_crtc_disable_vblank()
318 MASK(1), 1); in ade_irq_handler()
700 MASK(1), 0); in ade_compositor_routing_disable()
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| D | dw_dsi_reg.h | 10 #define MASK(x) (BIT(x) - 1) macro
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| /drivers/dma/dw/ |
| D | core.c | 124 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
125 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
490 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
491 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
514 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
515 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in dw_dma_interrupt()
516 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_interrupt()
525 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
526 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
527 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
[all …]
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 130 #define MASK(x) (BIT(x) - 1) macro
135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
161 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
175 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
182 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
189 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
[all …]
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| /drivers/scsi/ |
| D | vmw_pvscsi.h | 33 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
412 #define PVSCSI_INTR_CMPL_MASK MASK(2)
416 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
418 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
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| /drivers/gpu/drm/i915/ |
| D | i915_syncmap.c | 33 #define MASK (KSYNCMAP - 1) macro
114 return (id >> p->height) & MASK; in __sync_branch_idx()
121 return id & MASK; in __sync_leaf_idx()
305 idx = p->prefix >> (above - SHIFT) & MASK; in __sync_set()
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| /drivers/tty/ |
| D | n_tty.c | 130 #define MASK(x) ((x) & (N_TTY_BUF_SIZE - 1)) macro
632 while (MASK(ldata->echo_commit) != MASK(tail)) { in __process_echoes()
643 if (MASK(ldata->echo_commit) == MASK(tail + 1)) in __process_echoes()
656 if (MASK(ldata->echo_commit) == MASK(tail + 2)) in __process_echoes()
1009 while (MASK(ldata->read_head) != MASK(ldata->canon_head)) { in eraser()
1017 MASK(head) != MASK(ldata->canon_head)); in eraser()
1059 while (MASK(tail) != MASK(ldata->canon_head)) { in eraser()
1334 while (MASK(tail) != MASK(ldata->read_head)) { in n_tty_receive_char_special()
2490 while (MASK(head) != MASK(tail)) { in inq_canon()
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| /drivers/dma/ |
| D | idma64.c | 41 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); in idma64_off()
42 channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); in idma64_off()
43 channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); in idma64_off()
44 channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); in idma64_off()
45 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); in idma64_off()
71 channel_set_bit(idma64, MASK(XFER), idma64c->mask); in idma64_chan_init()
72 channel_set_bit(idma64, MASK(ERROR), idma64c->mask); in idma64_chan_init()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | cursor.c | 46 MASK(NV_CIO_CRE_HCUR_ASI) | in nv04_cursor_set_offset()
52 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); in nv04_cursor_set_offset()
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| D | hw.h | 31 #define MASK(field) ( \ macro
35 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
379 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
381 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
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| /drivers/gpu/drm/hisilicon/kirin/kirin/ |
| D | dw_drm_dsi.c | 265 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); in dsi_set_phy_timer()
266 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); in dsi_set_phy_timer()
267 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
269 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
271 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), in dsi_set_phy_timer()
273 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), in dsi_set_phy_timer()
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| /drivers/scsi/aic7xxx/aicasm/ |
| D | aicasm_symbol.c | 101 case MASK: in symbol_delete()
243 case MASK: in symlist_add()
501 case MASK: in symtable_dump()
628 case MASK: in symtable_dump()
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| /drivers/char/xilinx_hwicap/ |
| D | xilinx_hwicap.c | 127 .MASK = 6,
152 .MASK = 6,
177 .MASK = 6,
202 .MASK = 6,
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| D | xilinx_hwicap.h | 131 u32 MASK; member
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| /drivers/platform/x86/ |
| D | compal-laptop.c | 369 #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \ argument
373 return sprintf(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \
382 ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \
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